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[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_byte_ctrl.v] - Rev 75


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Rev Log message Author Age Path
68 New directory structure. root 5309d 23h /i2c/trunk/rtl/verilog/i2c_master_byte_ctrl.v
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 5359d 01h /i2c/trunk/rtl/verilog/i2c_master_byte_ctrl.v
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7156d 10h /i2c/trunk/rtl/verilog/i2c_master_byte_ctrl.v
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.
rherveille 7349d 14h /i2c/trunk/rtl/verilog/i2c_master_byte_ctrl.v
29 Core is now a Multimaster I2C controller rherveille 7575d 06h /i2c/trunk/rtl/verilog/i2c_master_byte_ctrl.v
27 Cleaned up code rherveille 7600d 23h /i2c/trunk/rtl/verilog/i2c_master_byte_ctrl.v
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.
rherveille 7991d 09h /i2c/trunk/rtl/verilog/i2c_master_byte_ctrl.v
13 Fixed some synthesis warnings. rherveille 8002d 13h /i2c/trunk/rtl/verilog/i2c_master_byte_ctrl.v
10 Created new directory structure.
Added Verilog version.
rherveille 8033d 09h /i2c/trunk/rtl/verilog/i2c_master_byte_ctrl.v

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