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[/] [i2c/] [trunk/] [rtl/] [vhdl/] - Rev 65

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Rev	Log message	Author	Age	Path
65	Changed wb_adr_i from unsigned to std_logic_vector	rherveille	5573d 16h	/i2c/trunk/rtl/vhdl/
64	Added SCL clock synchronization logic Fixed slave_wait signal generation	rherveille	5573d 17h	/i2c/trunk/rtl/vhdl/
60	Added missing semicolons ';' on endif	rherveille	6405d 15h	/i2c/trunk/rtl/vhdl/
59	fixed short scl high pulse after clock stretch	rherveille	6410d 16h	/i2c/trunk/rtl/vhdl/
53	Fixed previous fix :) Made a variable vs signal mistake.	rherveille	7292d 15h	/i2c/trunk/rtl/vhdl/
52	Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.	rherveille	7292d 16h	/i2c/trunk/rtl/vhdl/
51	Fixed simulation issue when writing to CR register	rherveille	7346d 17h	/i2c/trunk/rtl/vhdl/
48	Fixed a bug in the arbitration-lost signal generation. VHDL version only.	rherveille	7362d 19h	/i2c/trunk/rtl/vhdl/
47	Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.	rherveille	7371d 15h	/i2c/trunk/rtl/vhdl/
39	Forgot an 'end if' :-/	rherveille	7561d 12h	/i2c/trunk/rtl/vhdl/
38	Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. Fixed a potential bug in the byte controller's host-acknowledge generation.	rherveille	7564d 20h	/i2c/trunk/rtl/vhdl/
35	Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.	rherveille	7750d 03h	/i2c/trunk/rtl/vhdl/
34	Fixed a few 'arbitration lost' bugs. VHDL version only.	rherveille	7754d 01h	/i2c/trunk/rtl/vhdl/
31	Core is now a Multimaster I2C controller.	rherveille	7790d 11h	/i2c/trunk/rtl/vhdl/
28	* empty log message *	rherveille	7816d 05h	/i2c/trunk/rtl/vhdl/
27	Cleaned up code	rherveille	7816d 05h	/i2c/trunk/rtl/vhdl/
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7847d 09h	/i2c/trunk/rtl/vhdl/
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	7984d 19h	/i2c/trunk/rtl/vhdl/
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8201d 16h	/i2c/trunk/rtl/vhdl/
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8206d 15h	/i2c/trunk/rtl/vhdl/

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[/] [i2c/] [trunk/] [rtl/] [vhdl/] - Rev 65

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