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[/] [i2c/] [trunk/] [rtl/] [vhdl/] - Rev 76

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Rev Log message Author Age Path
31 Core is now a Multimaster I2C controller. rherveille 7176d 07h /i2c/trunk/rtl/vhdl/
28 *** empty log message *** rherveille 7202d 00h /i2c/trunk/rtl/vhdl/
27 Cleaned up code rherveille 7202d 00h /i2c/trunk/rtl/vhdl/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7233d 05h /i2c/trunk/rtl/vhdl/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7370d 15h /i2c/trunk/rtl/vhdl/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 7587d 12h /i2c/trunk/rtl/vhdl/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.
rherveille 7592d 11h /i2c/trunk/rtl/vhdl/
10 Created new directory structure.
Added Verilog version.
rherveille 7634d 10h /i2c/trunk/rtl/vhdl/

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