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[/] [i2c/] [trunk/] [rtl/] [vhdl/] - Rev 76


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Rev Log message Author Age Path
76 Updated filter_cnt generation rherveille 4503d 03h /i2c/trunk/rtl/vhdl
75 Fixed sSDA generation rherveille 4508d 23h /i2c/trunk/rtl/vhdl
72 Fixed AL generation
Added median filter on SDA and SCL inputs
rherveille 4647d 20h /i2c/trunk/rtl/vhdl
71 Fixed double wishbone write in a single access rherveille 4647d 20h /i2c/trunk/rtl/vhdl
68 New directory structure. root 4956d 14h /i2c/trunk/rtl/vhdl
67 Fixed slave_wait clocked event syntax rherveille 4989d 16h /i2c/trunk/rtl/vhdl
66 Fixed type iscl_oen instead of scl_oen rherveille 5004d 16h /i2c/trunk/rtl/vhdl
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 5005d 02h /i2c/trunk/rtl/vhdl
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 5005d 02h /i2c/trunk/rtl/vhdl
60 Added missing semicolons ';' on endif rherveille 5837d 00h /i2c/trunk/rtl/vhdl
59 fixed short scl high pulse after clock stretch rherveille 5842d 02h /i2c/trunk/rtl/vhdl
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 6724d 00h /i2c/trunk/rtl/vhdl
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 6724d 01h /i2c/trunk/rtl/vhdl
51 Fixed simulation issue when writing to CR register rherveille 6778d 02h /i2c/trunk/rtl/vhdl
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 6794d 05h /i2c/trunk/rtl/vhdl
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 6803d 01h /i2c/trunk/rtl/vhdl
39 Forgot an 'end if' :-/ rherveille 6992d 22h /i2c/trunk/rtl/vhdl
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.
rherveille 6996d 05h /i2c/trunk/rtl/vhdl
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7181d 12h /i2c/trunk/rtl/vhdl
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7185d 10h /i2c/trunk/rtl/vhdl

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