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[/] [i2c/] [trunk/] [rtl/] [vhdl/] [i2c_master_bit_ctrl.vhd] - Rev 22

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22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7957d 09h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.
rherveille 8179d 05h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd

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