OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [rtl/] [vhdl/] [i2c_master_bit_ctrl.vhd] - Rev 24

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
24 Fixed some reported minor start/stop generation timing issuess. rherveille 6971d 09h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7108d 20h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.
rherveille 7330d 15h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.