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Rev Log message Author Age Path
68 New directory structure. root 5386d 10h /i2c/trunk
67 Fixed slave_wait clocked event syntax rherveille 5419d 12h /trunk
66 Fixed type iscl_oen instead of scl_oen rherveille 5434d 11h /trunk
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 5434d 21h /trunk
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 5434d 22h /trunk
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 5434d 22h /trunk
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 5435d 12h /trunk
61 Removed synopsys link; it's not used rherveille 6089d 23h /trunk
60 Added missing semicolons ';' on endif rherveille 6266d 20h /trunk
59 fixed short scl high pulse after clock stretch rherveille 6271d 21h /trunk
58 fixed (n)ack generation rherveille 6303d 23h /trunk
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 6303d 23h /trunk
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 6856d 21h /trunk
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 6857d 23h /trunk
54 Fixed scl, sda delay. rherveille 6857d 23h /trunk
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7153d 20h /trunk
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7153d 21h /trunk
51 Fixed simulation issue when writing to CR register rherveille 7207d 22h /trunk
50 *** empty log message *** rherveille 7222d 16h /trunk
49 Added testbench rherveille 7222d 17h /trunk

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