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[/] [i2c/] [trunk] - Rev 68

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Rev Log message Author Age Path
68 New directory structure. root 5524d 18h /i2c/trunk
67 Fixed slave_wait clocked event syntax rherveille 5557d 20h /trunk
66 Fixed type iscl_oen instead of scl_oen rherveille 5572d 20h /trunk
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 5573d 06h /trunk
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation		 rherveille 5573d 06h /trunk
63 Added clock synchronization logic
Fixed slave_wait signal		 rherveille 5573d 06h /trunk
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits		 rherveille 5573d 20h /trunk
61 Removed synopsys link; it's not used rherveille 6228d 08h /trunk
60 Added missing semicolons ';' on endif rherveille 6405d 05h /trunk
59 fixed short scl high pulse after clock stretch rherveille 6410d 06h /trunk
58 fixed (n)ack generation rherveille 6442d 08h /trunk
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal		 rherveille 6442d 08h /trunk
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.		 rherveille 6995d 05h /trunk
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.		 rherveille 6996d 07h /trunk
54 Fixed scl, sda delay. rherveille 6996d 07h /trunk
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7292d 05h /trunk
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7292d 06h /trunk
51 Fixed simulation issue when writing to CR register rherveille 7346d 06h /trunk
50 *** empty log message *** rherveille 7361d 01h /trunk
49 Added testbench rherveille 7361d 01h /trunk
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7362d 09h /trunk
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7371d 05h /trunk
46 Fixed slave address MSB='1' bug rherveille 7446d 06h /trunk
45 Added slave address configurability rherveille 7446d 06h /trunk
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7531d 08h /trunk
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7541d 06h /trunk
39 Forgot an 'end if' :-/ rherveille 7561d 02h /trunk
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7564d 10h /trunk
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.		 rherveille 7601d 01h /trunk
36 Fixed cmd_ack generation item (no bug). rherveille 7716d 02h /trunk

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