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Rev Log message Author Age Path
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.
rherveille 7585d 00h /
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.
rherveille 7585d 00h /
13 Fixed some synthesis warnings. rherveille 7596d 04h /
12 no message rherveille 7601d 19h /
11 Changed RST_LVL define to parameter. rherveille 7605d 03h /
10 Created new directory structure.
Added Verilog version.
rherveille 7626d 23h /
9 Created directory structure (documentation, vhdl, verilog) rherveille 7696d 18h /
8 Created directory structure (documentation, vhdl, verilog) rherveille 7696d 18h /
7 added some remarks, fixed some sensitivity lists rherveille 7765d 21h /
6 fixed typo txt -> txr rherveille 7770d 01h /
5 fixed an incomplete sensitivity list on assign_dato process rherveille 7776d 23h /
4 WISHBONE I2C Master Core: initial release rherveille 7829d 02h /
3 This commit was manufactured by cvs2svn to create tag 'first'. 7891d 02h /
2 initial release rherveille 7891d 02h /
1 Standard project directories initialized by cvs2svn. 7891d 02h /

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