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Rev Log message Author Age Path
17 C-include file.
Initial release
rherveille 7370d 14h /
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 7382d 13h /
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.
rherveille 7387d 12h /
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.
rherveille 7387d 12h /
13 Fixed some synthesis warnings. rherveille 7398d 16h /
12 no message rherveille 7404d 07h /
11 Changed RST_LVL define to parameter. rherveille 7407d 15h /
10 Created new directory structure.
Added Verilog version.
rherveille 7429d 11h /
9 Created directory structure (documentation, vhdl, verilog) rherveille 7499d 06h /
8 Created directory structure (documentation, vhdl, verilog) rherveille 7499d 06h /
7 added some remarks, fixed some sensitivity lists rherveille 7568d 09h /
6 fixed typo txt -> txr rherveille 7572d 13h /
5 fixed an incomplete sensitivity list on assign_dato process rherveille 7579d 11h /
4 WISHBONE I2C Master Core: initial release rherveille 7631d 14h /
3 This commit was manufactured by cvs2svn to create tag 'first'. 7693d 14h /
2 initial release rherveille 7693d 14h /
1 Standard project directories initialized by cvs2svn. 7693d 14h /

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