OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] - Rev 47

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7344d 08h /
46 Fixed slave address MSB='1' bug rherveille 7419d 09h /
45 Added slave address configurability rherveille 7419d 09h /
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7504d 12h /
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7504d 12h /
42 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7514d 10h /
41 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7514d 10h /
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7514d 10h /
39 Forgot an 'end if' :-/ rherveille 7534d 05h /
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.
rherveille 7537d 13h /
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.
rherveille 7574d 05h /
36 Fixed cmd_ack generation item (no bug). rherveille 7689d 06h /
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7722d 20h /
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7726d 18h /
33 Fixed a bug in the Command Register declaration. rherveille 7749d 03h /
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.
rherveille 7759d 03h /
31 Core is now a Multimaster I2C controller. rherveille 7763d 04h /
30 Small code simplifications rherveille 7763d 04h /
29 Core is now a Multimaster I2C controller rherveille 7763d 05h /
28 *** empty log message *** rherveille 7788d 22h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.