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Rev	Log message	Author	Age	Path
71	Fixed double wishbone write in a single access	rherveille	5208d 03h	/
70	Added old uploaded documents to new repository.	root	5516d 06h	/
69	Added old uploaded documents to new repository.	root	5516d 21h	/
68	New directory structure.	root	5516d 21h	/
67	Fixed slave_wait clocked event syntax	rherveille	5550d 00h	/
66	Fixed type iscl_oen instead of scl_oen	rherveille	5564d 23h	/
65	Changed wb_adr_i from unsigned to std_logic_vector	rherveille	5565d 09h	/
64	Added SCL clock synchronization logic Fixed slave_wait signal generation	rherveille	5565d 09h	/
63	Added clock synchronization logic Fixed slave_wait signal	rherveille	5565d 09h	/
62	Fixed synopsys miss spell (synopsis) Fixed cr[0] register width Fixed ! usage instead of ~ Fixed bit controller parameter width to 18bits	rherveille	5565d 23h	/
61	Removed synopsys link; it's not used	rherveille	6220d 11h	/
60	Added missing semicolons ';' on endif	rherveille	6397d 08h	/
59	fixed short scl high pulse after clock stretch	rherveille	6402d 09h	/
58	fixed (n)ack generation	rherveille	6434d 11h	/
57	fixed short scl high pulse after clock stretch fixed slave model not returning correct '(n)ack' signal	rherveille	6434d 11h	/
56	Fixed Tsu:sta timing check. Added Thd:sta timing check.	rherveille	6987d 08h	/
55	Fixed register overwrite issue. Removed full_case pragma, replaced it by a default statement.	rherveille	6988d 10h	/
54	Fixed scl, sda delay.	rherveille	6988d 10h	/
53	Fixed previous fix :) Made a variable vs signal mistake.	rherveille	7284d 08h	/
52	Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.	rherveille	7284d 09h	/

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[/] - Rev 71

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