URL https://opencores.org/ocsvn/light8080/light8080/trunk

Subversion Repositories light8080

[/] - Rev 86

Rev	Log message	Author	Age	Path
66	Adding interrupt example code to the Verilog implementation. An interrupt controller was added to the sample SOC module and a sample code was added to the "hello.c" example code.	motilito	5119d 11h	/
65	Adding Verilog initial version to the svn. Added the c80 Small-C compiler and AS80 assembler.	motilito	5130d 19h	/
64	BUG FIX: Flags CY and AC were not clear by logic instructions Added new flag to microcode: clr_acy Used new flag to clear AC and CY flags unconditonally Modified microcode for XR, OR and AN* to use new flag Modified microcode assembler to support new flag Addex explaination of new flag to documentation Old fix that worked only for XR* instructions removed Test bench tb0 modified to test CY clearance minimally (AC untested!) Pre-generated vhel test bench tb0 altered accordingly	ja_rd	5139d 19h	/
63	Modified syntax of ARGV parameter for compatibility to later versions of Perl	ja_rd	5139d 19h	/
62	Changed all hard tabs to spaces as preamble to a minor refactor	ja_rd	5140d 05h	/
61	Basic demo updated: main entity name changed to keep synthesis too happy	ja_rd	5508d 06h	/
60	Fixed nasty typo in pin constraints file (clock input)	ja_rd	5512d 11h	/
59	tabs to spaces	ja_rd	5536d 19h	/
58	tabs to spaces	ja_rd	5536d 19h	/
57	removed unfinished CPM demo files	ja_rd	5721d 09h	/