Rev |
Log message |
Author |
Age |
Path |
113 |
minsoc-install.sh & minsoc-configure.sh:
-aware of location of configure.sh script
configure.sh:
-does not block on patch error
spartan3e_starter_kit & spartan3e_starter_kit_eth:
-or1200_defines.v updated
prj:
-src/blackboxes/or1200_top.v adjusted to or1200_rel1
-Makefile had a typo regarding altera vhdl files |
rfajardo |
5015d 05h |
/ |
112 |
Updating installation & configuration scripts. |
rfajardo |
5015d 20h |
/ |
111 |
minsoc-install.sh: DIR_TO_INSTALL is required before using beautify.sh |
rfajardo |
5015d 21h |
/ |
110 |
Fixing several minor issues with the system:
-minsoc-install splitted into installation and configuration
-minsoc-configure.sh can be used to configure a fresh checked out system
-configure script used by both minsoc-configure.sh and minsoc-install.sh to configure
-rtl/verilog: svn externals fixed
-or1200 rolled back to release-1.0
-prj/scripts:
-Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
-Altera was differentiating it in script
-now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
-altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.
-prj/src: or1200_top.prj downdated to definition of or1200_v1 |
rfajardo |
5015d 21h |
/ |
109 |
Creating a branche for release candidate 1.0. |
rfajardo |
5015d 23h |
/ |
108 |
Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.
Icarus Verilog and Altera synthesis are working as well. Job done! |
rfajardo |
5016d 02h |
/ |
107 |
Adding setup batch script for Altera synthesis on Windows.
prj/scripts/altprj.sh has now to check if it is run from cygwin in order to re-formulate the path to windows system.
Maybe the other scripts have to be updated too. This will be checked soon. |
rfajardo |
5016d 05h |
/ |
106 |
Installation script was checking the ENV variable before setting it. |
rfajardo |
5016d 08h |
/ |
105 |
Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. |
rfajardo |
5016d 10h |
/ |
104 |
Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools) |
rfajardo |
5023d 08h |
/ |
103 |
But the file is called gdb-6.8a.tar.bz2, so tar must be run on that name. |
rfajardo |
5025d 23h |
/ |
102 |
GNU GDB FTP has renamed gdb-6.8 package to gdb-6.8a package. Uncompressed it remains gdb-6.8, so no other changes to script are necessary. |
rfajardo |
5025d 23h |
/ |
101 |
Documentation, wiki's address updated. |
rfajardo |
5051d 11h |
/ |
100 |
syn/altera/minsoc_top.qsf: I thought this file was being generated now as project file description. But it is merely a synthesis configuration file and must be here. File re-added. |
rfajardo |
5060d 09h |
/ |
99 |
backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. |
rfajardo |
5060d 09h |
/ |
98 |
Removing deprecated minsoc_top.qsf file. |
rfajardo |
5060d 10h |
/ |
97 |
As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. |
rfajardo |
5060d 10h |
/ |
96 |
Some files needed for Altera synthesis |
javieralso |
5060d 21h |
/ |
95 |
Makefile for Altera FPGAs fixed |
javieralso |
5062d 00h |
/ |
94 |
Fix bug in minsoc_top.prj for Altera synthesis |
javieralso |
5064d 08h |
/ |
93 |
Support for Altera synthesis. It needs some tune, but it works fine |
javieralso |
5064d 11h |
/ |
92 |
backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. |
rfajardo |
5065d 09h |
/ |
91 |
prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. |
rfajardo |
5065d 10h |
/ |
90 |
After minsoc_top.prj update, make regenerated src and xst files. |
rfajardo |
5066d 01h |
/ |
89 |
minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. |
rfajardo |
5066d 02h |
/ |
88 |
Project structure, Xilinx Makefiles and simulation working. |
rfajardo |
5066d 02h |
/ |
87 |
Synchronizing scripts to behave exactly the same. |
rfajardo |
5066d 03h |
/ |
86 |
Updating configure script messages. |
rfajardo |
5066d 03h |
/ |
85 |
Central project definition under prj. Synthesis and simulation take their project files from here. |
rfajardo |
5066d 03h |
/ |
84 |
syn/blackboxes/eth_top.v:
-module is now called ethmac instead of eth_top
-eth_defines.v is now called ethmac_defines.v |
rfajardo |
5067d 04h |
/ |