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Rev Log message Author Age Path
107 Adding setup batch script for Altera synthesis on Windows.

prj/scripts/ has now to check if it is run from cygwin in order to re-formulate the path to windows system.

Maybe the other scripts have to be updated too. This will be checked soon.
rfajardo 3376d 21h /
106 Installation script was checking the ENV variable before setting it. rfajardo 3377d 00h /
105 Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. rfajardo 3377d 02h /
104 Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/ splitted in:
(they generate the input files in the right format for simulation tools)
rfajardo 3384d 01h /
103 But the file is called gdb-6.8a.tar.bz2, so tar must be run on that name. rfajardo 3386d 16h /
102 GNU GDB FTP has renamed gdb-6.8 package to gdb-6.8a package. Uncompressed it remains gdb-6.8, so no other changes to script are necessary. rfajardo 3386d 16h /
101 Documentation, wiki's address updated. rfajardo 3412d 04h /
100 syn/altera/minsoc_top.qsf: I thought this file was being generated now as project file description. But it is merely a synthesis configuration file and must be here. File re-added. rfajardo 3421d 02h /
99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 3421d 02h /
98 Removing deprecated minsoc_top.qsf file. rfajardo 3421d 02h /

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