| Rev |
Log message |
Author |
Age |
Path |
| 131 |
Renaming testbench modules. Adding to ifdefs without which the testbench generation can fail. |
rfajardo |
4829d 08h |
/ |
| 130 |
minsoc_bench.v: task test_eth has to be phased out together with the ETHERNET definition. If there is no ETHERNET, test_eth cannot be defined. |
rfajardo |
4829d 11h |
/ |
| 129 |
Removing bugs introduced when splitting clocks and reset.
1) NEGATIVE_RESET or POSITIVE_RESET were missing as definition on minsoc_bench_clock.v (include minsoc_defines.v).
2) wait for reset on minsoc_bench.v to assert design_ready |
rfajardo |
4829d 22h |
/ |
| 128 |
Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v. |
rfajardo |
4829d 22h |
/ |
| 127 |
Removing redundant simulation output. |
rfajardo |
4830d 05h |
/ |
| 126 |
Updating information about simulation time for Ethernet test. |
rfajardo |
4830d 05h |
/ |
| 125 |
Adjusting testbench messages. Creating tasks for firmware tests. |
rfajardo |
4830d 05h |
/ |
| 124 |
Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever. |
rfajardo |
4830d 07h |
/ |
| 123 |
Renaming reg final to firmware_size. Final is a keyword for Verilator. |
rfajardo |
4830d 12h |
/ |
| 122 |
Renaming minsoc-configure.sh to minsoc-setup.sh. |
rfajardo |
4836d 01h |
/ |
| 121 |
Asserting svn:executable properties of modelsim/*.bat scripts.
Including corrected patch for advanced debug system watchpoints under utils/setup. Configure script updated to use this instead of advanced debug system patches. This will remain so until the patch is corrected. The previous line still has the correct command. |
rfajardo |
4836d 03h |
/ |
| 120 |
ethmac.prj: a file was missing |
rfajardo |
4836d 05h |
/ |
| 119 |
Tricking Subversion to accept bat files that are now executable. |
rfajardo |
4836d 06h |
/ |
| 118 |
Configure scripts for Xilinx devices updated. All of them require to update or1200_defines.v. The non-standard part uses now the variable $BOARD to print that this board require non-standard update of files. |
rfajardo |
4836d 06h |
/ |
| 117 |
spartan3e_starter_kit designs require DUALPORT from or1200_defines.v to be active instead of GENERIC. |
rfajardo |
4836d 07h |
/ |
| 116 |
Configure scripts were trying to copy/patch projects files before creating them. Ordering is correct now. |
rfajardo |
4836d 07h |
/ |
| 115 |
configure.sh script dir aware.
minsoc-install.sh logging to script dir. |
rfajardo |
4836d 08h |
/ |
| 114 |
Installation and Configuration scripts can be run out of any directory.
They assume they are going to process the files and directories found in the directory they are run from. |
rfajardo |
4836d 08h |
/ |
| 113 |
minsoc-install.sh & minsoc-configure.sh:
-aware of location of configure.sh script
configure.sh:
-does not block on patch error
spartan3e_starter_kit & spartan3e_starter_kit_eth:
-or1200_defines.v updated
prj:
-src/blackboxes/or1200_top.v adjusted to or1200_rel1
-Makefile had a typo regarding altera vhdl files |
rfajardo |
4836d 08h |
/ |
| 112 |
Updating installation & configuration scripts. |
rfajardo |
4836d 23h |
/ |
| 111 |
minsoc-install.sh: DIR_TO_INSTALL is required before using beautify.sh |
rfajardo |
4837d 00h |
/ |
| 110 |
Fixing several minor issues with the system:
-minsoc-install splitted into installation and configuration
-minsoc-configure.sh can be used to configure a fresh checked out system
-configure script used by both minsoc-configure.sh and minsoc-install.sh to configure
-rtl/verilog: svn externals fixed
-or1200 rolled back to release-1.0
-prj/scripts:
-Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
-Altera was differentiating it in script
-now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
-altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.
-prj/src: or1200_top.prj downdated to definition of or1200_v1 |
rfajardo |
4837d 01h |
/ |
| 109 |
Creating a branche for release candidate 1.0. |
rfajardo |
4837d 02h |
/ |
| 108 |
Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.
Icarus Verilog and Altera synthesis are working as well. Job done! |
rfajardo |
4837d 05h |
/ |
| 107 |
Adding setup batch script for Altera synthesis on Windows.
prj/scripts/altprj.sh has now to check if it is run from cygwin in order to re-formulate the path to windows system.
Maybe the other scripts have to be updated too. This will be checked soon. |
rfajardo |
4837d 08h |
/ |
| 106 |
Installation script was checking the ENV variable before setting it. |
rfajardo |
4837d 11h |
/ |
| 105 |
Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. |
rfajardo |
4837d 13h |
/ |
| 104 |
Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools) |
rfajardo |
4844d 12h |
/ |
| 103 |
But the file is called gdb-6.8a.tar.bz2, so tar must be run on that name. |
rfajardo |
4847d 03h |
/ |
| 102 |
GNU GDB FTP has renamed gdb-6.8 package to gdb-6.8a package. Uncompressed it remains gdb-6.8, so no other changes to script are necessary. |
rfajardo |
4847d 03h |
/ |
