URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

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Rev	Log message	Author	Age	Path
136	Installation on Ubuntu-11.10 has shown that a binary called makeinfo is required to install GDB. This binary can be installed on Ubuntu by installing the package texinfo.	rfajardo	4538d 18h	/
135	Installation on Ubuntu-11.10 has shown that package texinfo is required to compiled GDB. This package installs the binary makeinfo.	rfajardo	4538d 18h	/
134	run_sim.bat for ModelSim updated to acquire the firmware_size for command line input when running the testbench.	rfajardo	4545d 22h	/
133	Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again. Applying Rubén Diez patch to avoid warnings on firmware load for simulation.	rfajardo	4546d 00h	/
132	ModelSim simulation, running top_module minsoc_bench_clock now, instead of minsoc_bench.	rfajardo	4549d 19h	/
131	Renaming testbench modules. Adding to ifdefs without which the testbench generation can fail.	rfajardo	4549d 19h	/
130	minsoc_bench.v: task test_eth has to be phased out together with the ETHERNET definition. If there is no ETHERNET, test_eth cannot be defined.	rfajardo	4549d 22h	/
129	Removing bugs introduced when splitting clocks and reset. 1) NEGATIVE_RESET or POSITIVE_RESET were missing as definition on minsoc_bench_clock.v (include minsoc_defines.v). 2) wait for reset on minsoc_bench.v to assert design_ready	rfajardo	4550d 09h	/
128	Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v.	rfajardo	4550d 10h	/
127	Removing redundant simulation output.	rfajardo	4550d 16h	/
126	Updating information about simulation time for Ethernet test.	rfajardo	4550d 16h	/
125	Adjusting testbench messages. Creating tasks for firmware tests.	rfajardo	4550d 16h	/
124	Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever.	rfajardo	4550d 18h	/
123	Renaming reg final to firmware_size. Final is a keyword for Verilator.	rfajardo	4550d 23h	/
122	Renaming minsoc-configure.sh to minsoc-setup.sh.	rfajardo	4556d 12h	/
121	Asserting svn:executable properties of modelsim/*.bat scripts. Including corrected patch for advanced debug system watchpoints under utils/setup. Configure script updated to use this instead of advanced debug system patches. This will remain so until the patch is corrected. The previous line still has the correct command.	rfajardo	4556d 14h	/
120	ethmac.prj: a file was missing	rfajardo	4556d 17h	/
119	Tricking Subversion to accept bat files that are now executable.	rfajardo	4556d 17h	/
118	Configure scripts for Xilinx devices updated. All of them require to update or1200_defines.v. The non-standard part uses now the variable $BOARD to print that this board require non-standard update of files.	rfajardo	4556d 17h	/
117	spartan3e_starter_kit designs require DUALPORT from or1200_defines.v to be active instead of GENERIC.	rfajardo	4556d 18h	/

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[/] - Rev 136

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