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158 Adding de2_115_board port, thanks to Richard Hasha.

Support to JSP (JTAG Serial Port) working well. Also provided by Richard Hasha.

Different interconnect configurations per board are not straightforward on MinSoC. New added modules or definitions for addresses have to be carried over to other boards. Furthermore, extra modules can be shared among all projects. Thus, it is better to have this centralized:
-Removing interconnect configuration from minsoc_defines.v. There is an interconnect_defines.v file on rtl/verilog. The software counterpart is interconnect.h on sw/drivers.

Including a jsp firmware. It is basically the uart firmware but using JSP instead. Added to all board configure scripts to be compiled on configuration.

prj/srcs extended to include jsp and interconnec_defines.v.

spartan3e_starter_kit_eth lost UART (does not fit) and uses JSP instead now.
rfajardo 3144d 22h /
157 Removed obsolete file; the changes in this version have been merged into
the mainline advanced debug system version 3.0 and higher.
nyawn 3150d 17h /
156 Added hardware watchpoint indicators to debug unit break input, to allow
the debugger to break when a hardware watchpoint is triggered.
nyawn 3150d 17h /
155 Decreased wait time, for faster simulations. nyawn 3150d 17h /
154 Modified to use the new autotools support in the advanced debug system v3.0. nyawn 3150d 17h /
153 Updating installation script to download minsoc from this branche, verilator, instead of rc-1.0. rfajardo 3183d 06h /
152 Roll back to retrieve minsoc from branches/rc-1.0. rfajardo 3183d 07h /
151 Creating tag release-1.0 from revision 150 of branches/rc-1.0. rfajardo 3183d 07h /
150 Updating installation script to retrieve minsoc from tags/release-1.0. rfajardo 3183d 07h /
149 Merging differences of release candidate 1.0 revision 140:148 with trunk. rfajardo 3183d 07h /
148 Renaming minsoc_wave.lxt to minsoc_wave.lxt2 for correctness. rfajardo 3188d 03h /
147 Updating minsoc_bench.v to correctly acquire uart data.

Uart drivers: when an end of line character was sent, the driver appended a carriage return to it. This is not necessary and has been removed.
-Eth and Uart firmwares also had a carriage return after the end of line, also removed.

Minsoc_bench_defines.v: Renaming VCD_OUTPUT define to WAVEFORM_OUTPUT

run_bench: selecting -lxt2 for waveform output format. This output format size is 10 times smaller than vcd.

minsoc-install.sh: lxt2 output format requires that Icarus Verilog be installed with zlib support. For that, we now check if zlib is supported on script run.
rfajardo 3188d 05h /
146 Importing 'Xilinx Microblaze Dev. Kit 1600E Edition' board configuration directory. ConX. 3188d 11h /
145 minsoc_bench_core.v and minsoc_bench_clock.v left only on verilator branche. It will develop there until it is ported for inclusion into trunk. RC-1.0 is now clean of it. rfajardo 3188d 20h /
144 Updating configure scripts. Calling make into the right directories now. rfajardo 3189d 06h /
143 Compiling firmwares in board configuration scripts instead of on global minsoc setup. rfajardo 3189d 06h /
142 Updating configure.sh:
1) we don't patch the trunk version.
2) it is better to re-compile the firmwares on reconfiguration. So compiling firmwares went to configure scripts instead.

backend/xxx/configure: compiling firmwares here now.
rfajardo 3189d 06h /
141 Merging with rc-1.0 revision 140. I doubt rc-1.0 will still change much in the last days. rfajardo 3189d 07h /
140 Including required modules for verilator simulation. rfajardo 3189d 07h /
139 Creating a verilator branche. rfajardo 3189d 07h /
138 DIR_TO_INSTALL creation using wizard ConX. 3189d 20h /
137 Removing uncomplete support for ml509 and not working support for spartan3e_starter_kit_eth (area constraint cannot be reached). rfajardo 3190d 07h /
136 Installation on Ubuntu-11.10 has shown that a binary called makeinfo is required to install GDB. This binary can be installed on Ubuntu by installing the package texinfo. rfajardo 3197d 02h /
135 Installation on Ubuntu-11.10 has shown that package texinfo is required to compiled GDB. This package installs the binary makeinfo. rfajardo 3197d 02h /
134 run_sim.bat for ModelSim updated to acquire the firmware_size for command line input when running the testbench. rfajardo 3204d 06h /
133 Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again.

Applying Rubén Diez patch to avoid warnings on firmware load for simulation.
rfajardo 3204d 08h /
132 ModelSim simulation, running top_module minsoc_bench_clock now, instead of minsoc_bench. rfajardo 3208d 03h /
131 Renaming testbench modules. Adding to ifdefs without which the testbench generation can fail. rfajardo 3208d 03h /
130 minsoc_bench.v: task test_eth has to be phased out together with the ETHERNET definition. If there is no ETHERNET, test_eth cannot be defined. rfajardo 3208d 06h /
129 Removing bugs introduced when splitting clocks and reset.
1) NEGATIVE_RESET or POSITIVE_RESET were missing as definition on minsoc_bench_clock.v (include minsoc_defines.v).
2) wait for reset on minsoc_bench.v to assert design_ready
rfajardo 3208d 17h /

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