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106 Installation script was checking the ENV variable before setting it. rfajardo 3896d 11h /minsoc/
105 Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. rfajardo 3896d 13h /minsoc/
104 Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools)
rfajardo 3903d 12h /minsoc/
103 But the file is called gdb-6.8a.tar.bz2, so tar must be run on that name. rfajardo 3906d 03h /minsoc/
102 GNU GDB FTP has renamed gdb-6.8 package to gdb-6.8a package. Uncompressed it remains gdb-6.8, so no other changes to script are necessary. rfajardo 3906d 03h /minsoc/
101 Documentation, wiki's address updated. rfajardo 3931d 15h /minsoc/
100 syn/altera/minsoc_top.qsf: I thought this file was being generated now as project file description. But it is merely a synthesis configuration file and must be here. File re-added. rfajardo 3940d 13h /minsoc/
99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 3940d 13h /minsoc/
98 Removing deprecated minsoc_top.qsf file. rfajardo 3940d 13h /minsoc/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 3940d 13h /minsoc/
96 Some files needed for Altera synthesis javieralso 3941d 00h /minsoc/
95 Makefile for Altera FPGAs fixed javieralso 3942d 03h /minsoc/
94 Fix bug in minsoc_top.prj for Altera synthesis javieralso 3944d 12h /minsoc/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 3944d 15h /minsoc/
92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 3945d 12h /minsoc/
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 3945d 13h /minsoc/
90 After minsoc_top.prj update, make regenerated src and xst files. rfajardo 3946d 05h /minsoc/
89 minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. rfajardo 3946d 05h /minsoc/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 3946d 05h /minsoc/
87 Synchronizing scripts to behave exactly the same. rfajardo 3946d 06h /minsoc/
86 Updating configure script messages. rfajardo 3946d 06h /minsoc/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 3946d 07h /minsoc/
84 syn/blackboxes/eth_top.v:
-module is now called ethmac instead of eth_top
-eth_defines.v is now called ethmac_defines.v
rfajardo 3947d 07h /minsoc/
83 minsoc-install.sh: bzip2 program was being used, but its existance on target system was not being verified. It is now. rfajardo 3958d 13h /minsoc/
82 minsoc-install.sh: problems with copying the GNU Toolchain from download to tools. We uncompress the GNU Toolchain now once again to tools during the installation part. rfajardo 3961d 12h /minsoc/
81 Installation script complete, nice text feedback, output logs and better execution order. rfajardo 3961d 23h /minsoc/
80 Establishing a better Makefile system for firmwares. rfajardo 3964d 11h /minsoc/
79 minsoc-install.sh: rpath corrected.
required-cygwin-tools: updated
rfajardo 3965d 04h /minsoc/
78 minsoc-install.sh: Advanced JTAG bridge compilation needs to know where the dynamic libraries are on runtime. Patching (sed) the Makefile to compile it with the rpath to the libraries (libusb/libftdi). rfajardo 3965d 04h /minsoc/
77 New tool requirements for installing Icarus Verilog. rfajardo 3965d 04h /minsoc/

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