| Rev |
Log message |
Author |
Age |
Path |
| 109 |
Creating a branche for release candidate 1.0. |
rfajardo |
4424d 07h |
/minsoc/ |
| 108 |
Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.
Icarus Verilog and Altera synthesis are working as well. Job done! |
rfajardo |
4424d 10h |
/minsoc/ |
| 107 |
Adding setup batch script for Altera synthesis on Windows.
prj/scripts/altprj.sh has now to check if it is run from cygwin in order to re-formulate the path to windows system.
Maybe the other scripts have to be updated too. This will be checked soon. |
rfajardo |
4424d 13h |
/minsoc/ |
| 106 |
Installation script was checking the ENV variable before setting it. |
rfajardo |
4424d 16h |
/minsoc/ |
| 105 |
Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. |
rfajardo |
4424d 18h |
/minsoc/ |
| 104 |
Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools) |
rfajardo |
4431d 16h |
/minsoc/ |
| 103 |
But the file is called gdb-6.8a.tar.bz2, so tar must be run on that name. |
rfajardo |
4434d 08h |
/minsoc/ |
| 102 |
GNU GDB FTP has renamed gdb-6.8 package to gdb-6.8a package. Uncompressed it remains gdb-6.8, so no other changes to script are necessary. |
rfajardo |
4434d 08h |
/minsoc/ |
| 101 |
Documentation, wiki's address updated. |
rfajardo |
4459d 20h |
/minsoc/ |
| 100 |
syn/altera/minsoc_top.qsf: I thought this file was being generated now as project file description. But it is merely a synthesis configuration file and must be here. File re-added. |
rfajardo |
4468d 17h |
/minsoc/ |
| 99 |
backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. |
rfajardo |
4468d 17h |
/minsoc/ |
| 98 |
Removing deprecated minsoc_top.qsf file. |
rfajardo |
4468d 18h |
/minsoc/ |
| 97 |
As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. |
rfajardo |
4468d 18h |
/minsoc/ |
| 96 |
Some files needed for Altera synthesis |
javieralso |
4469d 05h |
/minsoc/ |
| 95 |
Makefile for Altera FPGAs fixed |
javieralso |
4470d 08h |
/minsoc/ |
| 94 |
Fix bug in minsoc_top.prj for Altera synthesis |
javieralso |
4472d 17h |
/minsoc/ |
| 93 |
Support for Altera synthesis. It needs some tune, but it works fine |
javieralso |
4472d 19h |
/minsoc/ |
| 92 |
backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. |
rfajardo |
4473d 17h |
/minsoc/ |
| 91 |
prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. |
rfajardo |
4473d 18h |
/minsoc/ |
| 90 |
After minsoc_top.prj update, make regenerated src and xst files. |
rfajardo |
4474d 10h |
/minsoc/ |
