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Rev Log message Author Age Path
118 Configure scripts for Xilinx devices updated. All of them require to update or1200_defines.v. The non-standard part uses now the variable $BOARD to print that this board require non-standard update of files. rfajardo 3993d 20h /minsoc/
117 spartan3e_starter_kit designs require DUALPORT from or1200_defines.v to be active instead of GENERIC. rfajardo 3993d 20h /minsoc/
116 Configure scripts were trying to copy/patch projects files before creating them. Ordering is correct now. rfajardo 3993d 21h /minsoc/
115 configure.sh script dir aware.
minsoc-install.sh logging to script dir.
rfajardo 3993d 22h /minsoc/
114 Installation and Configuration scripts can be run out of any directory.
They assume they are going to process the files and directories found in the directory they are run from.
rfajardo 3993d 22h /minsoc/
113 minsoc-install.sh & minsoc-configure.sh:
-aware of location of configure.sh script
configure.sh:
-does not block on patch error

spartan3e_starter_kit & spartan3e_starter_kit_eth:
-or1200_defines.v updated

prj:
-src/blackboxes/or1200_top.v adjusted to or1200_rel1
-Makefile had a typo regarding altera vhdl files
rfajardo 3993d 22h /minsoc/
112 Updating installation & configuration scripts. rfajardo 3994d 13h /minsoc/
111 minsoc-install.sh: DIR_TO_INSTALL is required before using beautify.sh rfajardo 3994d 14h /minsoc/
110 Fixing several minor issues with the system:
-minsoc-install splitted into installation and configuration
-minsoc-configure.sh can be used to configure a fresh checked out system
-configure script used by both minsoc-configure.sh and minsoc-install.sh to configure

-rtl/verilog: svn externals fixed
-or1200 rolled back to release-1.0

-prj/scripts:
-Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
-Altera was differentiating it in script
-now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
-altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.

-prj/src: or1200_top.prj downdated to definition of or1200_v1
rfajardo 3994d 14h /minsoc/
109 Creating a branche for release candidate 1.0. rfajardo 3994d 16h /minsoc/
108 Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.

Icarus Verilog and Altera synthesis are working as well. Job done!
rfajardo 3994d 19h /minsoc/
107 Adding setup batch script for Altera synthesis on Windows.

prj/scripts/altprj.sh has now to check if it is run from cygwin in order to re-formulate the path to windows system.

Maybe the other scripts have to be updated too. This will be checked soon.
rfajardo 3994d 22h /minsoc/
106 Installation script was checking the ENV variable before setting it. rfajardo 3995d 01h /minsoc/
105 Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. rfajardo 3995d 03h /minsoc/
104 Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools)
rfajardo 4002d 01h /minsoc/
103 But the file is called gdb-6.8a.tar.bz2, so tar must be run on that name. rfajardo 4004d 16h /minsoc/
102 GNU GDB FTP has renamed gdb-6.8 package to gdb-6.8a package. Uncompressed it remains gdb-6.8, so no other changes to script are necessary. rfajardo 4004d 16h /minsoc/
101 Documentation, wiki's address updated. rfajardo 4030d 04h /minsoc/
100 syn/altera/minsoc_top.qsf: I thought this file was being generated now as project file description. But it is merely a synthesis configuration file and must be here. File re-added. rfajardo 4039d 02h /minsoc/
99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 4039d 02h /minsoc/
98 Removing deprecated minsoc_top.qsf file. rfajardo 4039d 03h /minsoc/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 4039d 03h /minsoc/
96 Some files needed for Altera synthesis javieralso 4039d 14h /minsoc/
95 Makefile for Altera FPGAs fixed javieralso 4040d 17h /minsoc/
94 Fix bug in minsoc_top.prj for Altera synthesis javieralso 4043d 02h /minsoc/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 4043d 04h /minsoc/
92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 4044d 02h /minsoc/
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 4044d 03h /minsoc/
90 After minsoc_top.prj update, make regenerated src and xst files. rfajardo 4044d 19h /minsoc/
89 minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. rfajardo 4044d 19h /minsoc/

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