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99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 3784d 20h /minsoc/
98 Removing deprecated minsoc_top.qsf file. rfajardo 3784d 20h /minsoc/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 3784d 20h /minsoc/
96 Some files needed for Altera synthesis javieralso 3785d 07h /minsoc/
95 Makefile for Altera FPGAs fixed javieralso 3786d 10h /minsoc/
94 Fix bug in minsoc_top.prj for Altera synthesis javieralso 3788d 19h /minsoc/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 3788d 22h /minsoc/
92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 3789d 20h /minsoc/
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 3789d 20h /minsoc/
90 After minsoc_top.prj update, make regenerated src and xst files. rfajardo 3790d 12h /minsoc/

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