OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] - Rev 123

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
103 But the file is called gdb-6.8a.tar.bz2, so tar must be run on that name. rfajardo 3382d 06h /minsoc/
102 GNU GDB FTP has renamed gdb-6.8 package to gdb-6.8a package. Uncompressed it remains gdb-6.8, so no other changes to script are necessary. rfajardo 3382d 06h /minsoc/
101 Documentation, wiki's address updated. rfajardo 3407d 18h /minsoc/
100 syn/altera/minsoc_top.qsf: I thought this file was being generated now as project file description. But it is merely a synthesis configuration file and must be here. File re-added. rfajardo 3416d 16h /minsoc/
99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 3416d 16h /minsoc/
98 Removing deprecated minsoc_top.qsf file. rfajardo 3416d 17h /minsoc/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 3416d 17h /minsoc/
96 Some files needed for Altera synthesis javieralso 3417d 04h /minsoc/
95 Makefile for Altera FPGAs fixed javieralso 3418d 07h /minsoc/
94 Fix bug in minsoc_top.prj for Altera synthesis javieralso 3420d 15h /minsoc/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.