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Rev Log message Author Age Path
116 Configure scripts were trying to copy/patch projects files before creating them. Ordering is correct now. rfajardo 4556d 21h /minsoc/
115 configure.sh script dir aware.
minsoc-install.sh logging to script dir.		 rfajardo 4556d 21h /minsoc/
114 Installation and Configuration scripts can be run out of any directory.
They assume they are going to process the files and directories found in the directory they are run from.		 rfajardo 4556d 22h /minsoc/
113 minsoc-install.sh & minsoc-configure.sh:
-aware of location of configure.sh script
configure.sh:
-does not block on patch error

spartan3e_starter_kit & spartan3e_starter_kit_eth:
-or1200_defines.v updated

prj:
-src/blackboxes/or1200_top.v adjusted to or1200_rel1
-Makefile had a typo regarding altera vhdl files		 rfajardo 4556d 22h /minsoc/
112 Updating installation & configuration scripts. rfajardo 4557d 13h /minsoc/
111 minsoc-install.sh: DIR_TO_INSTALL is required before using beautify.sh rfajardo 4557d 14h /minsoc/
110 Fixing several minor issues with the system:
-minsoc-install splitted into installation and configuration
-minsoc-configure.sh can be used to configure a fresh checked out system
-configure script used by both minsoc-configure.sh and minsoc-install.sh to configure

-rtl/verilog: svn externals fixed
-or1200 rolled back to release-1.0

-prj/scripts:
-Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
-Altera was differentiating it in script
-now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
-altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.

-prj/src: or1200_top.prj downdated to definition of or1200_v1		 rfajardo 4557d 14h /minsoc/
109 Creating a branche for release candidate 1.0. rfajardo 4557d 16h /minsoc/
108 Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.

Icarus Verilog and Altera synthesis are working as well. Job done!		 rfajardo 4557d 19h /minsoc/
107 Adding setup batch script for Altera synthesis on Windows.

prj/scripts/altprj.sh has now to check if it is run from cygwin in order to re-formulate the path to windows system.

Maybe the other scripts have to be updated too. This will be checked soon.		 rfajardo 4557d 22h /minsoc/

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