URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] - Rev 149

Rev	Log message	Author	Age	Path
129	Removing bugs introduced when splitting clocks and reset. 1) NEGATIVE_RESET or POSITIVE_RESET were missing as definition on minsoc_bench_clock.v (include minsoc_defines.v). 2) wait for reset on minsoc_bench.v to assert design_ready	rfajardo	4556d 13h	/minsoc/
128	Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v.	rfajardo	4556d 14h	/minsoc/
127	Removing redundant simulation output.	rfajardo	4556d 20h	/minsoc/
126	Updating information about simulation time for Ethernet test.	rfajardo	4556d 20h	/minsoc/
125	Adjusting testbench messages. Creating tasks for firmware tests.	rfajardo	4556d 21h	/minsoc/
124	Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever.	rfajardo	4556d 22h	/minsoc/
123	Renaming reg final to firmware_size. Final is a keyword for Verilator.	rfajardo	4557d 03h	/minsoc/
122	Renaming minsoc-configure.sh to minsoc-setup.sh.	rfajardo	4562d 17h	/minsoc/
121	Asserting svn:executable properties of modelsim/*.bat scripts. Including corrected patch for advanced debug system watchpoints under utils/setup. Configure script updated to use this instead of advanced debug system patches. This will remain so until the patch is corrected. The previous line still has the correct command.	rfajardo	4562d 18h	/minsoc/
120	ethmac.prj: a file was missing	rfajardo	4562d 21h	/minsoc/