URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] - Rev 151

Rev	Log message	Author	Age	Path
131	Renaming testbench modules. Adding to ifdefs without which the testbench generation can fail.	rfajardo	4556d 02h	/minsoc/
130	minsoc_bench.v: task test_eth has to be phased out together with the ETHERNET definition. If there is no ETHERNET, test_eth cannot be defined.	rfajardo	4556d 05h	/minsoc/
129	Removing bugs introduced when splitting clocks and reset. 1) NEGATIVE_RESET or POSITIVE_RESET were missing as definition on minsoc_bench_clock.v (include minsoc_defines.v). 2) wait for reset on minsoc_bench.v to assert design_ready	rfajardo	4556d 16h	/minsoc/
128	Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v.	rfajardo	4556d 17h	/minsoc/
127	Removing redundant simulation output.	rfajardo	4556d 23h	/minsoc/
126	Updating information about simulation time for Ethernet test.	rfajardo	4556d 23h	/minsoc/
125	Adjusting testbench messages. Creating tasks for firmware tests.	rfajardo	4556d 23h	/minsoc/
124	Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever.	rfajardo	4557d 01h	/minsoc/
123	Renaming reg final to firmware_size. Final is a keyword for Verilator.	rfajardo	4557d 06h	/minsoc/
122	Renaming minsoc-configure.sh to minsoc-setup.sh.	rfajardo	4562d 19h	/minsoc/