URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] - Rev 154

Rev	Log message	Author	Age	Path
134	run_sim.bat for ModelSim updated to acquire the firmware_size for command line input when running the testbench.	rfajardo	4546d 22h	/minsoc/
133	Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again. Applying Rubén Diez patch to avoid warnings on firmware load for simulation.	rfajardo	4546d 23h	/minsoc/
132	ModelSim simulation, running top_module minsoc_bench_clock now, instead of minsoc_bench.	rfajardo	4550d 19h	/minsoc/
131	Renaming testbench modules. Adding to ifdefs without which the testbench generation can fail.	rfajardo	4550d 19h	/minsoc/
130	minsoc_bench.v: task test_eth has to be phased out together with the ETHERNET definition. If there is no ETHERNET, test_eth cannot be defined.	rfajardo	4550d 21h	/minsoc/
129	Removing bugs introduced when splitting clocks and reset. 1) NEGATIVE_RESET or POSITIVE_RESET were missing as definition on minsoc_bench_clock.v (include minsoc_defines.v). 2) wait for reset on minsoc_bench.v to assert design_ready	rfajardo	4551d 08h	/minsoc/
128	Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v.	rfajardo	4551d 09h	/minsoc/
127	Removing redundant simulation output.	rfajardo	4551d 15h	/minsoc/
126	Updating information about simulation time for Ethernet test.	rfajardo	4551d 15h	/minsoc/
125	Adjusting testbench messages. Creating tasks for firmware tests.	rfajardo	4551d 16h	/minsoc/