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[/] [minsoc/] - Rev 167

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Rev Log message Author Age Path
147 Updating minsoc_bench.v to correctly acquire uart data.

Uart drivers: when an end of line character was sent, the driver appended a carriage return to it. This is not necessary and has been removed.
-Eth and Uart firmwares also had a carriage return after the end of line, also removed.

Minsoc_bench_defines.v: Renaming VCD_OUTPUT define to WAVEFORM_OUTPUT

run_bench: selecting -lxt2 for waveform output format. This output format size is 10 times smaller than vcd.

minsoc-install.sh: lxt2 output format requires that Icarus Verilog be installed with zlib support. For that, we now check if zlib is supported on script run.
rfajardo 3111d 16h /minsoc/
146 Importing 'Xilinx Microblaze Dev. Kit 1600E Edition' board configuration directory. ConX. 3111d 22h /minsoc/
145 minsoc_bench_core.v and minsoc_bench_clock.v left only on verilator branche. It will develop there until it is ported for inclusion into trunk. RC-1.0 is now clean of it. rfajardo 3112d 07h /minsoc/
144 Updating configure scripts. Calling make into the right directories now. rfajardo 3112d 17h /minsoc/
143 Compiling firmwares in board configuration scripts instead of on global minsoc setup. rfajardo 3112d 17h /minsoc/
142 Updating configure.sh:
1) we don't patch the trunk version.
2) it is better to re-compile the firmwares on reconfiguration. So compiling firmwares went to configure scripts instead.

backend/xxx/configure: compiling firmwares here now.
rfajardo 3112d 17h /minsoc/
141 Merging with rc-1.0 revision 140. I doubt rc-1.0 will still change much in the last days. rfajardo 3112d 17h /minsoc/
140 Including required modules for verilator simulation. rfajardo 3112d 18h /minsoc/
139 Creating a verilator branche. rfajardo 3112d 18h /minsoc/
138 DIR_TO_INSTALL creation using wizard ConX. 3113d 07h /minsoc/

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