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Rev Log message Author Age Path
18 Deprecated comments removed from the file listing files. rfajardo 5271d 01h /minsoc/
17 Ethernet testbench speed penalty solved. Now Ethernet of testbench and minsoc can be enabled by only uncommenting `define ETHERNET on minsoc_defines.v.

send_mac, get_mac and uart_send tasks have been included/improved. Also a testbench, which works for both included firmwares is added. (eth and uart)

If ETHERNET is defined for the SoC, both firmwares will complete successfully. If not, the eth firmware will stall when trying to access the Ethernet module.		 rfajardo 5272d 20h /minsoc/
16 Further initialization improvement of non-used signals, setting interrupt signals to 0 if module is not used. rfajardo 5278d 00h /minsoc/
15 Including verified pinout for external spi flash on spartan3a dsp kit to its correspondent ucf constraint file. rfajardo 5278d 17h /minsoc/
14 Wishbone error signal of Ethernet core was not tied to ground if Ethernet was disabled. Solved now. rfajardo 5287d 00h /minsoc/
13 Updating spartan3e_starter_kit.ucf so that it does not deliver errors on mapping. Moreover it has been changed to off the shelf only have uart support. Ethernet support and generic JTAG can be added by uncommenting the corresponding lines. rfajardo 5288d 01h /minsoc/
12 1) spi_top.v:
-TX_NEGEDGE bug reported and recommended solution by Blaise Gassend. (Thank you)
2) minsoc howto extended to:
-synthesis of minsoc for Spartan3E Starter Kit with Ethernet
3) spartan3e_starter_kit.ucf changed:
-it had problems regarding pin definitions and IO logic types for mapping and place&route. Working flawless now.		 rfajardo 5290d 16h /minsoc/
11 External interrupt processing was being run multiple times because:
-external level interrupts have to be cleared
-internal interrupt status register has to be cleared
Since internal interrupt status register was being cleared before external level interrupts clearance, these internal interrupt status was being overwritten inbetween.

Solution:
-move status register reset to end of interrupt handler instead of beginning.

Testbench signal uart_srx initialized now.		 rfajardo 5297d 20h /minsoc/
10 Added a file containing models for each FPGA memory instances used in or1200. The file is in bench/verilog/sim_lib/fpga_memory_primitives.v.

With it, people who change the or1200_defines.v inside of the project structure will still be able to simulate, using house-made models, not from manufacturers.

minsoc_bench.v had to be extended by the task, init_fpga_memory, to initialize the dual or two port memories instances of or1200. This has to be done based on the type of memory used, so many different instantiations based on definitions. Somehow or1200 expects all memory values to be 0 upon start, so this is necessary.		 rfajardo 5311d 20h /minsoc/
9 Tiny change to testbench gain:
-uart_srx is now reg for future testbench serial input to SoC.		 rfajardo 5313d 18h /minsoc/

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