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50 Removing unused firmware files, respective to or1ksim actually.

Removing the inclusion of the removed file mc.h in reset.S, probably required by or1ksim at some point.

Reworked except.S to use a macro instead of repeating the same procedure 16 times or so. Explanation added to the macro as a leading comment.
rfajardo 5004d 23h /minsoc/
49 Language correction for README.txt. rfajardo 5006d 21h /minsoc/
48 Clear some old docs that are already ported to MinSOC's Wiki ConX. 5006d 22h /minsoc/
47 Firmware updated to work with gcc-4.5. It is actually working just fine and gcc-4.5 assembly code seems a lot cleaner.

I noticed that by increasing the free stack space for the interrupt handler by 130 made the resulting firmware not work. I assume it is because 130 is not aligned 130%4 = 2 and the stack simply does not work then. Instead I'm freeing the previous 116 plus 128 (for 32 registers as mentioned by Jeremy) and it works.
rfajardo 5007d 20h /minsoc/
46 Including an explanation of what has to be updated on gpio to port it smoothly to minsoc. rfajardo 5008d 01h /minsoc/
45 A more stable version ConX. 5008d 16h /minsoc/
44 Fixing some bugs. But it still works only in Debian/Ubuntu ConX. 5008d 17h /minsoc/
43 Making some changes to MinSOC install script ConX. 5009d 14h /minsoc/
42 Tagging release 0.9 of MinSoC. rfajardo 5013d 21h /minsoc/
41 Including setup scripts to install all required tools to work with minsoc and to download all required sources. Thanks for the contribution of Xanthopoulos Constantinos. rfajardo 5013d 21h /minsoc/
40 Commiting a contributions directory, which has raw contributions of users. These contributions still have to be adapted to the system in order to work well. However, some users are certainly able to work with these versions.

FAQ: -added new idea to circumvent onboard DLC9 cable problem for adv_jtag_bridge
INSTALL: -gives a hint on how to install the system for Windows
HOWTO: -explains what a ucf file is and how to create it

backend: now we have the first contribution of a ucf file for the ML509 board (thanks to Matthew Hick)

Documentation: THESIS.txt explains to users, willing to tweak/understand the inner behavior of the OR1200 implementation of OpenRISC, what to read in order to get this information.
rfajardo 5019d 19h /minsoc/
39 FAQ:
-Adv_jtag_bridge self test fails?
-included now SoC flow mistakes
-forgetting to upload the bitfile
-leaving clock unconnected
-older information is now under "Known Issues" right below of SoC flow mistakes

Software:
-eth: included eth.h is from drivers and not from this directory. eth.h from this directory is old and has been removed.
-uart: included uart.h is from drivers and not from this directory. uart.h from this directory is old and has been removed.
rfajardo 5084d 12h /minsoc/
38 Small update to HOWTO: advices now to also include the ucf (pinout) file, for forgetful people :-).

FAQ: Added another option (hint) as a solution for people with on-board Xilinx USB cables, which do not reset.

uart.c: now uses the IRQ line definition instead of the line number directly.
rfajardo 5119d 11h /minsoc/
37 README.txt added, describing the installation and set-up processes. Also describing to use the FAQ or forum when you have problems and finally to read minsoc.pdf (the documentation) to understand the system after everything works, to know what to do next.

Clean-up of sw/utils, removing unused sources and files.

Update of sw/drivers/eth.c, direct casting to avoid compile warnings.

FAQ extended and with more links to the threads giving the solutions.

Synthesis examples inform that the firmware tweak for Spartan3E Starter Kit using Ethernet only works for system version up to 35.

minsoc.pdf and webpage now uses FPGA generic and specific codes instead of FPGA independent and dependent codes, because it suits it better.
rfajardo 5149d 22h /minsoc/
36 utils: -adding a 32 to 8 bit Wishbone bridge to connect 8 bit modules to the MinSoC interconnect.
-adding a Linux driver for parallel cables for the adv_jtag_bridge. It circumvents the necessity of privilege to run adv_jtag_bridge with cables xpc3 and xess.

sw/support: support library has been made completely standalone. That means, it is now independent from uClib and/or newlib. Thanks to Wojciech A. Koszek for his contribution on this.

sw/drivers: a driver library has been included, which supply drivers for the OpenRISC timer; and for UART, Ethernet, I2C, and CAN modules from OpenCores.

sw/uart and sw/eth: they don't provide code to control the UART and Ethernet controllers anymore. They use the drivers library instead.

Documentation:
-FAQ extended:
-table of contents
-explanation of how to use the 32 to 8 bit Wishbone bridge
-how to make adv_jtag_bridge work without privilege requirement for xess or xpc3
-explanation of locking problem of xpc_usb cable
-explanation of what to do if the cable is built on-board
-INSTALL:
-patching of gdb only required if version is 6.8, explanation on FAQ now.
-HOWTO:
-instruct to compile drivers library
-remove line numbers information on what to edit, better leave it to be found only by the informed context.
-adv_jtag_bridge execution now without 'sudo'. Note included that 'sudo' is required for Linux and xess or xpc3. Reference to FAQ to avoid this requirement.
rfajardo 5150d 18h /minsoc/
35 minsoc.pdf: -adjusting the date on the page header of MinSoC documentation. It was correct on the front and revision pages, now header adjusted accordingly. rfajardo 5155d 12h /minsoc/
34 start_server changed: '-t' option of adv_jtag_bridge for vpi connection on simulation removed. or1200_v3 will not pass on CPU self test.

FAQ completed with asked questions since Februrary 2010.

INSTALL informs bsdl files only have to be copied to home directory for Xilinx devices.

synthesis_examples title includes Minimal OpenRISC System on Chip.
rfajardo 5164d 20h /minsoc/
33 Start-up Starter, included in the MinSoC top file, has been updated to three-phase instruction output; instruction assertion, acknowledge assertion, and next instruction with acknowledge deassertion.

Previously it was two-phase with next instruction, instruction assertion and acknowledge assertion together, and acknowledge deassertion.

That is required by the new Wishbone master interface used by OpenRISC release 3.
rfajardo 5172d 22h /minsoc/
32 Documentation revision 1.1, thanks to Wojciech A. Koszek for many comments on it.

Also updating howto, splitint it in INSTALL, HOWTO, FAQ and synthesis_examples, so it should be more clear now what to do when and not to try too much when you don't need. Like everyone was trying to debug the simulation but didn't even test the regular simulation before. Again thanks to Wojciech A. Koszek for his view on this matter.
rfajardo 5186d 20h /minsoc/
31 Adaption to or1200_r3. It is still important to change or1200_defines.v:
-`define OR1200_BOOT_ADR 32'hf0000100 to `define OR1200_BOOT_ADR 32'h00000100
rfajardo 5242d 03h /minsoc/

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