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85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4840d 16h /minsoc
84 syn/blackboxes/eth_top.v:
-module is now called ethmac instead of eth_top
-eth_defines.v is now called ethmac_defines.v
rfajardo 4841d 16h /minsoc
83 minsoc-install.sh: bzip2 program was being used, but its existance on target system was not being verified. It is now. rfajardo 4852d 22h /minsoc
82 minsoc-install.sh: problems with copying the GNU Toolchain from download to tools. We uncompress the GNU Toolchain now once again to tools during the installation part. rfajardo 4855d 21h /minsoc
81 Installation script complete, nice text feedback, output logs and better execution order. rfajardo 4856d 08h /minsoc
80 Establishing a better Makefile system for firmwares. rfajardo 4858d 20h /minsoc
79 minsoc-install.sh: rpath corrected.
required-cygwin-tools: updated
rfajardo 4859d 13h /minsoc
78 minsoc-install.sh: Advanced JTAG bridge compilation needs to know where the dynamic libraries are on runtime. Patching (sed) the Makefile to compile it with the rpath to the libraries (libusb/libftdi). rfajardo 4859d 13h /minsoc
77 New tool requirements for installing Icarus Verilog. rfajardo 4859d 14h /minsoc
76 Including a script allowing the installation of MinSoC and all its required tools.

It should be working for all Linuxes and Cygwin.
rfajardo 4859d 14h /minsoc
75 Adapting minsoc_top.v and minsoc_verilog_files.txt to new names for top modules and define file of ethmac ip core. rfajardo 4866d 14h /minsoc
74 or1200.h includes a CLABLE macro which uses __USER_LABEL_PREFIX__(from compiler defined macro) to find out if we need the underscore as prefix to reference C functions (its assembly labels) or not.

except.S and reset.S use CLABLE to call externally defined C functions.

This should avoid problems compiling firmware with old or new toolchain.

support/common.mk updated, reset-nocache.o and reset-icdc.o are dependent on or1200.h
rfajardo 4959d 12h /minsoc
73 Makefile does not automatic clean anymore. In Windows rm -f leads to errors and abort synthesis.

minsoc/syn/setup.bat added. Asks for Xilinx settings32|64.bat script and completely implements MinSoC. On completion or error, it holds window open until user input ENTER.

minsoc/sim/modelsim/: *.bat holds window open until user input ENTER.
run_sim.bat asks for target firmware, check if it exists before running simulator. Holds window open and output error message if not found. Does not hold for simulator.
rfajardo 4959d 17h /minsoc
72 Adding Windows batch files to run a Modelsim simulation.
-prepare_modelsim.bat, compile_design.bat, run_sim.bat
rfajardo 4959d 19h /minsoc
71 Modelsim whines about missing timescales:
-minsoc_bench.v, minsoc_memory_model.v and dbg_comm_vpi.v updated to include timescale.v

modelsim simulation working under Windows. Modelsim PE Student Edition 10.0a

Simulation<->adv_jtag_bridge<->gdb communication not working perfectly. I believe VPI module has to be recompiled, used pre-compiled one for now.
rfajardo 4959d 21h /minsoc
70 Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it.

Removing timescale definition of minsoc_bench_defines.v files.

Creating a modelsim simulation directory. Everything is working under Linux. For Windows, run_sim.sh has to be changed:
-pli ../../bench/verilog/vpi/jp-io-vpi.so
to:
-pli ../../bench/verilog/vpi/jp-io-vpi.dll

These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi.
rfajardo 4959d 21h /minsoc
69 backend update:
-minsoc_bench_defines.v
-gcc-opt.mk
Both files should now be under minsoc/backend to proper system functionality.
backend subdirectories have been given those files. Configure script updated accordingly.

They are searched there from system scripts and Makefiles.
-sim/bin/minsoc_verilog_files.txt has the files for Icarus Verilog, minsoc_bench_defines.v is now referenced from backend directory.
-sw/support/Makefile.inc now references to gcc-opt.mk inside backend.

backend/spartan3e_starter_kit_eth:
-It is the system configuration for Spartan 3E Starter Kit with Ethernet.
rfajardo 4964d 13h /minsoc
68 Still one configuration mismatch on minsoc_defines.v:
-MEMORY_ADR_WIDTH now 15
-orp.ld is defined accordingly
rfajardo 4966d 17h /minsoc
67 Constraint file for backend spartan3a_dsp_kit.ucf was configured to include the STARTUP module.

This module is not enabled under the respective minsoc_defines.v. Thus, its pins had to be commented out.
rfajardo 4966d 17h /minsoc
66 spartan3e_starter_kit requires special configuration of or1200_r3.

For that, configure script was specially adapted and that is reported on script execution.

For release-1.0 of MinSoC this should not be required, because or1200_r1 already has the
required configuration.
rfajardo 4966d 18h /minsoc
65 Files missing in the last commit.
backend/std/configure
sw: eth, uart and driver Makefiles
rfajardo 4966d 19h /minsoc
64 firmware makefiles:
-every firmware makefile has now complete dependency. This also includes dependency on files under minsoc/backend (target specific files). That means, that if some target specific header changes, the support library dependent on it will be compiled. That will always happen, even if you compile the uart firmware. In other words, if you want to use uart firmware, you can always simply compile uart by issuing make all. If anything has changed, backend files, support library, drivers, it will update everything for you.
-TODO: dependency can be automatic created by using make together with gcc. Use it instead of declaring all dependencies manually.

Makefile system for synthesis:
-the dependency for every implementation step has been checked and is working fine.
-Makefile plus support files have been moved to minsoc/syn/src
-make usage is still under syn through files generated by backend bashscripts
Backend:
-files under backend are target specific files used for the system to work
-firmware compilation
-system simulation
-system implementation
-This directory is populated by visiting one of its subdirectories and typing ./configure

backend/spartan3a_dsp_kit:
-working on FPGA

backend/spartan3e_starter_kit:
-has to be tested

backend/ml509:
-missing files have to be copied and adapted, configure script has to be copied and adapted

backend/std:
-include files necessary for firmware compilation and system configuration
-it does not include files for synthesis and is not synthesizable
rfajardo 4966d 20h /minsoc
63 Adding a functional synthesis Makefile system. Still needs a reviews and enhancements, but at least it is something. rfajardo 4970d 14h /minsoc
62 Wrapping different family modules of same manufacturer in a single module.

minsoc_clock_manager.v: uses fpga manufacturer wrappers

xilinx_dcm.v: selects between different Xilinx FPGA families and implements the module

altera_pll.v: selects between different Altera FPGA families and implements the module
rfajardo 4970d 21h /minsoc
61 Removing supposely defined external function, which don't exist anymore. rfajardo 4970d 22h /minsoc
60 Selection of memory model or implementation memory is now made on minsoc_bench_defines.v. It is done by a definition instead of including different files for simulation.

minsoc_bench_defines.v definition of reset level was not correct. It based the level decision on defineds POSITIVE_RESET or NEGATIVE_RESET, which couldn't be defined by then, since minsoc_defines.v is not included in minsoc_bench_defines.v. The decision has been moved to minsoc_bench.v and made a localparam instead of a definition.
rfajardo 4971d 09h /minsoc
59 undefinition of NEGATIVE_RESET on minsoc_bench_defines.v cannot affect other inclusions of minsoc_defines.v. Instead, the testbench now works with the right reset level to avoid the implementation ordering problem. rfajardo 4971d 09h /minsoc
58 Standard definitions depended on implementation order. Now, this should be solved.

minsoc_bench_defines.v: when setting reset to be positive (`define POSITIVE_RESET), NEGATIVE_RESET is undefined. This override the implementation order, so that independent of it, POSITIVE_RESET will be used.

minsoc_defines.v: when setting GENERIC_FPGA, FPGA_TAP and FPGA_CLOCK_DIVISION are undefined. This way, even if FPGA_TAP would come prior to GENERIC_TAP on the correspondent implementation, GENERIC_TAP would still be selected.

IMPORTANT: GENERIC_MEMORY must still be implemented first on minsoc_onchip_ram.v, because FPGA's memory is automatically selected from other definitions and cannot be undefined a priori. Since some other memory types can be selected, there is no trivial solution. However, this shouldn't be a big problem, since the beginning of this file will probably not be modified.
rfajardo 4971d 10h /minsoc
57 If a FPGA manufacturer is selected, the FPGA families of other manufacturers are automatically ignored.

Some updated to comments.

CLOCK_DIVISOR back to 5. The number does not matter much, but 1 is a bad standard number, since it should never be selected. Comment says, use NO_CLOCK_DIVISION instead.

Changing standard FPGA back to Xilinx and Spartan3A. I'm only doing this because the synthesis examples page of wiki still assume this FPGA to be standardly selected.
rfajardo 4971d 10h /minsoc
56 Macros for all Altera family devices and pll instantiation javieralso 4978d 09h /minsoc

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