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Rev Log message Author Age Path
124 Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever. rfajardo 3311d 16h /minsoc/branches/
123 Renaming reg final to firmware_size. Final is a keyword for Verilator. rfajardo 3311d 21h /minsoc/branches/
122 Renaming minsoc-configure.sh to minsoc-setup.sh. rfajardo 3317d 10h /minsoc/branches/
121 Asserting svn:executable properties of modelsim/*.bat scripts.

Including corrected patch for advanced debug system watchpoints under utils/setup. Configure script updated to use this instead of advanced debug system patches. This will remain so until the patch is corrected. The previous line still has the correct command.
rfajardo 3317d 12h /minsoc/branches/
120 ethmac.prj: a file was missing rfajardo 3317d 14h /minsoc/branches/
119 Tricking Subversion to accept bat files that are now executable. rfajardo 3317d 15h /minsoc/branches/
118 Configure scripts for Xilinx devices updated. All of them require to update or1200_defines.v. The non-standard part uses now the variable $BOARD to print that this board require non-standard update of files. rfajardo 3317d 15h /minsoc/branches/
117 spartan3e_starter_kit designs require DUALPORT from or1200_defines.v to be active instead of GENERIC. rfajardo 3317d 16h /minsoc/branches/
116 Configure scripts were trying to copy/patch projects files before creating them. Ordering is correct now. rfajardo 3317d 16h /minsoc/branches/
115 configure.sh script dir aware.
minsoc-install.sh logging to script dir.
rfajardo 3317d 17h /minsoc/branches/

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