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Rev Log message Author Age Path
98 Removing deprecated minsoc_top.qsf file. rfajardo 4581d 00h /minsoc/branches/rc-1.0/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 4581d 00h /minsoc/branches/rc-1.0/
96 Some files needed for Altera synthesis javieralso 4581d 11h /minsoc/branches/rc-1.0/
95 Makefile for Altera FPGAs fixed javieralso 4582d 14h /minsoc/branches/rc-1.0/
94 Fix bug in minsoc_top.prj for Altera synthesis javieralso 4584d 23h /minsoc/branches/rc-1.0/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 4585d 01h /minsoc/branches/rc-1.0/
92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 4585d 23h /minsoc/branches/rc-1.0/
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 4586d 00h /minsoc/branches/rc-1.0/
90 After minsoc_top.prj update, make regenerated src and xst files. rfajardo 4586d 16h /minsoc/branches/rc-1.0/
89 minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. rfajardo 4586d 16h /minsoc/branches/rc-1.0/

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