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104 Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools)		 rfajardo 4566d 04h /minsoc/branches/rc-1.0/
103 But the file is called gdb-6.8a.tar.bz2, so tar must be run on that name. rfajardo 4568d 19h /minsoc/branches/rc-1.0/
102 GNU GDB FTP has renamed gdb-6.8 package to gdb-6.8a package. Uncompressed it remains gdb-6.8, so no other changes to script are necessary. rfajardo 4568d 19h /minsoc/branches/rc-1.0/
101 Documentation, wiki's address updated. rfajardo 4594d 07h /minsoc/branches/rc-1.0/
100 syn/altera/minsoc_top.qsf: I thought this file was being generated now as project file description. But it is merely a synthesis configuration file and must be here. File re-added. rfajardo 4603d 05h /minsoc/branches/rc-1.0/
99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 4603d 05h /minsoc/branches/rc-1.0/
98 Removing deprecated minsoc_top.qsf file. rfajardo 4603d 06h /minsoc/branches/rc-1.0/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 4603d 06h /minsoc/branches/rc-1.0/
96 Some files needed for Altera synthesis javieralso 4603d 17h /minsoc/branches/rc-1.0/
95 Makefile for Altera FPGAs fixed javieralso 4604d 20h /minsoc/branches/rc-1.0/

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