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[/] [minsoc/] [branches/] [rc-1.0/] - Rev 128

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108 Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.

Icarus Verilog and Altera synthesis are working as well. Job done!
rfajardo 3696d 21h /minsoc/branches/rc-1.0/
107 Adding setup batch script for Altera synthesis on Windows.

prj/scripts/altprj.sh has now to check if it is run from cygwin in order to re-formulate the path to windows system.

Maybe the other scripts have to be updated too. This will be checked soon.
rfajardo 3697d 00h /minsoc/branches/rc-1.0/
106 Installation script was checking the ENV variable before setting it. rfajardo 3697d 03h /minsoc/branches/rc-1.0/
105 Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. rfajardo 3697d 04h /minsoc/branches/rc-1.0/
104 Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools)
rfajardo 3704d 03h /minsoc/branches/rc-1.0/
103 But the file is called gdb-6.8a.tar.bz2, so tar must be run on that name. rfajardo 3706d 18h /minsoc/branches/rc-1.0/
102 GNU GDB FTP has renamed gdb-6.8 package to gdb-6.8a package. Uncompressed it remains gdb-6.8, so no other changes to script are necessary. rfajardo 3706d 18h /minsoc/branches/rc-1.0/
101 Documentation, wiki's address updated. rfajardo 3732d 06h /minsoc/branches/rc-1.0/
100 syn/altera/minsoc_top.qsf: I thought this file was being generated now as project file description. But it is merely a synthesis configuration file and must be here. File re-added. rfajardo 3741d 04h /minsoc/branches/rc-1.0/
99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 3741d 04h /minsoc/branches/rc-1.0/

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