| Rev |
Log message |
Author |
Age |
Path |
| 59 |
undefinition of NEGATIVE_RESET on minsoc_bench_defines.v cannot affect other inclusions of minsoc_defines.v. Instead, the testbench now works with the right reset level to avoid the implementation ordering problem. |
rfajardo |
4736d 22h |
/minsoc/branches/rc-1.0/ |
| 58 |
Standard definitions depended on implementation order. Now, this should be solved.
minsoc_bench_defines.v: when setting reset to be positive (`define POSITIVE_RESET), NEGATIVE_RESET is undefined. This override the implementation order, so that independent of it, POSITIVE_RESET will be used.
minsoc_defines.v: when setting GENERIC_FPGA, FPGA_TAP and FPGA_CLOCK_DIVISION are undefined. This way, even if FPGA_TAP would come prior to GENERIC_TAP on the correspondent implementation, GENERIC_TAP would still be selected.
IMPORTANT: GENERIC_MEMORY must still be implemented first on minsoc_onchip_ram.v, because FPGA's memory is automatically selected from other definitions and cannot be undefined a priori. Since some other memory types can be selected, there is no trivial solution. However, this shouldn't be a big problem, since the beginning of this file will probably not be modified. |
rfajardo |
4736d 22h |
/minsoc/branches/rc-1.0/ |
| 57 |
If a FPGA manufacturer is selected, the FPGA families of other manufacturers are automatically ignored.
Some updated to comments.
CLOCK_DIVISOR back to 5. The number does not matter much, but 1 is a bad standard number, since it should never be selected. Comment says, use NO_CLOCK_DIVISION instead.
Changing standard FPGA back to Xilinx and Spartan3A. I'm only doing this because the synthesis examples page of wiki still assume this FPGA to be standardly selected. |
rfajardo |
4736d 23h |
/minsoc/branches/rc-1.0/ |
| 56 |
Macros for all Altera family devices and pll instantiation |
javieralso |
4743d 21h |
/minsoc/branches/rc-1.0/ |
| 55 |
Adjusting Makefiles to compile correctly with new firmware updates.
1) except.o not included into libsupport.a.
2) libsupport.a linked to except.o, now in correct order: ld libsupport.a except.o -o executable (not the other way around)
3) int.c was not being compiled because of a #ifdef which is not set anywhere |
rfajardo |
4745d 06h |
/minsoc/branches/rc-1.0/ |
| 54 |
Moving spr_defs.h to or1200.h |
ConX. |
4745d 08h |
/minsoc/branches/rc-1.0/ |
| 53 |
Indentation, deleting redundant files and adding externals |
ConX. |
4745d 09h |
/minsoc/branches/rc-1.0/ |
| 52 |
Altera ALTPLL Megafunction Instantiation |
javieralso |
4753d 23h |
/minsoc/branches/rc-1.0/ |
| 51 |
sw/support/uart.c: Changing the order of writes to the Divisor Latch of UART. (Thanks Ramkumar) |
rfajardo |
4760d 12h |
/minsoc/branches/rc-1.0/ |
| 50 |
Removing unused firmware files, respective to or1ksim actually.
Removing the inclusion of the removed file mc.h in reset.S, probably required by or1ksim at some point.
Reworked except.S to use a macro instead of repeating the same procedure 16 times or so. Explanation added to the macro as a leading comment. |
rfajardo |
4772d 08h |
/minsoc/branches/rc-1.0/ |
| 49 |
Language correction for README.txt. |
rfajardo |
4774d 06h |
/minsoc/branches/rc-1.0/ |
| 48 |
Clear some old docs that are already ported to MinSOC's Wiki |
ConX. |
4774d 07h |
/minsoc/branches/rc-1.0/ |
| 47 |
Firmware updated to work with gcc-4.5. It is actually working just fine and gcc-4.5 assembly code seems a lot cleaner.
I noticed that by increasing the free stack space for the interrupt handler by 130 made the resulting firmware not work. I assume it is because 130 is not aligned 130%4 = 2 and the stack simply does not work then. Instead I'm freeing the previous 116 plus 128 (for 32 registers as mentioned by Jeremy) and it works. |
rfajardo |
4775d 05h |
/minsoc/branches/rc-1.0/ |
| 46 |
Including an explanation of what has to be updated on gpio to port it smoothly to minsoc. |
rfajardo |
4775d 10h |
/minsoc/branches/rc-1.0/ |
| 45 |
A more stable version |
ConX. |
4776d 01h |
/minsoc/branches/rc-1.0/ |
| 44 |
Fixing some bugs. But it still works only in Debian/Ubuntu |
ConX. |
4776d 02h |
/minsoc/branches/rc-1.0/ |
| 43 |
Making some changes to MinSOC install script |
ConX. |
4776d 23h |
/minsoc/branches/rc-1.0/ |
| 41 |
Including setup scripts to install all required tools to work with minsoc and to download all required sources. Thanks for the contribution of Xanthopoulos Constantinos. |
rfajardo |
4781d 06h |
/minsoc/branches/rc-1.0/ |
| 40 |
Commiting a contributions directory, which has raw contributions of users. These contributions still have to be adapted to the system in order to work well. However, some users are certainly able to work with these versions.
FAQ: -added new idea to circumvent onboard DLC9 cable problem for adv_jtag_bridge
INSTALL: -gives a hint on how to install the system for Windows
HOWTO: -explains what a ucf file is and how to create it
backend: now we have the first contribution of a ucf file for the ML509 board (thanks to Matthew Hick)
Documentation: THESIS.txt explains to users, willing to tweak/understand the inner behavior of the OR1200 implementation of OpenRISC, what to read in order to get this information. |
rfajardo |
4787d 04h |
/minsoc/branches/rc-1.0/ |
| 39 |
FAQ:
-Adv_jtag_bridge self test fails?
-included now SoC flow mistakes
-forgetting to upload the bitfile
-leaving clock unconnected
-older information is now under "Known Issues" right below of SoC flow mistakes
Software:
-eth: included eth.h is from drivers and not from this directory. eth.h from this directory is old and has been removed.
-uart: included uart.h is from drivers and not from this directory. uart.h from this directory is old and has been removed. |
rfajardo |
4851d 21h |
/minsoc/branches/rc-1.0/ |
