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[/] [minsoc/] [branches/] [rc-1.0/] - Rev 6

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6 No implementation relevant changes.

Testbench used generic memory from minsoc_onchip_ram.v has been changed to reflect the correct model of the FPGA's onchip rams: address register and write accesses are sensitive to rising clock edge.

Documentation updated to reflect another trial and next steps to speed up the memory access from 2 clocks to 1. The negated clock approach is not standard. The right way to do it would be to use the wishbone signals cti and bte and change the minsoc_onchip_ram_top.v.
rfajardo 5295d 07h /minsoc/branches/rc-1.0/
5 vpi path corrected in how to. rfajardo 5301d 06h /minsoc/branches/rc-1.0/
4 minsoc_bench.v had a big memory declaration to load the firmware, which was not necessary.

jp-io-vpi.vpi has to be compiled for different systems so removed from the project. Documentation now explains how to do it.

Documentation now includes:
-vpi module compilation
-gdb patch for adv_jtag_bridge
-ideas for future work on minsoc (To Do v.2)
rfajardo 5301d 06h /minsoc/branches/rc-1.0/
3 Changed documentation
-advice to compile sw/utils before compiling target software
rfajardo 5305d 04h /minsoc/branches/rc-1.0/
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 5305d 04h /minsoc/branches/rc-1.0/
1 The project was created and the structure was created root 5305d 06h /minsoc/branches/rc-1.0/

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