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57 If a FPGA manufacturer is selected, the FPGA families of other manufacturers are automatically ignored.

Some updated to comments.

CLOCK_DIVISOR back to 5. The number does not matter much, but 1 is a bad standard number, since it should never be selected. Comment says, use NO_CLOCK_DIVISION instead.

Changing standard FPGA back to Xilinx and Spartan3A. I'm only doing this because the synthesis examples page of wiki still assume this FPGA to be standardly selected.		 rfajardo 4744d 06h /minsoc/branches/rc-1.0/
56 Macros for all Altera family devices and pll instantiation javieralso 4751d 04h /minsoc/branches/rc-1.0/
55 Adjusting Makefiles to compile correctly with new firmware updates.

1) except.o not included into libsupport.a.
2) libsupport.a linked to except.o, now in correct order: ld libsupport.a except.o -o executable (not the other way around)
3) int.c was not being compiled because of a #ifdef which is not set anywhere		 rfajardo 4752d 13h /minsoc/branches/rc-1.0/
54 Moving spr_defs.h to or1200.h ConX. 4752d 14h /minsoc/branches/rc-1.0/
53 Indentation, deleting redundant files and adding externals ConX. 4752d 16h /minsoc/branches/rc-1.0/
52 Altera ALTPLL Megafunction Instantiation javieralso 4761d 06h /minsoc/branches/rc-1.0/
51 sw/support/uart.c: Changing the order of writes to the Divisor Latch of UART. (Thanks Ramkumar) rfajardo 4767d 19h /minsoc/branches/rc-1.0/
50 Removing unused firmware files, respective to or1ksim actually.

Removing the inclusion of the removed file mc.h in reset.S, probably required by or1ksim at some point.

Reworked except.S to use a macro instead of repeating the same procedure 16 times or so. Explanation added to the macro as a leading comment.		 rfajardo 4779d 15h /minsoc/branches/rc-1.0/
49 Language correction for README.txt. rfajardo 4781d 13h /minsoc/branches/rc-1.0/
48 Clear some old docs that are already ported to MinSOC's Wiki ConX. 4781d 14h /minsoc/branches/rc-1.0/

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