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85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4000d 15h /minsoc/branches/rc-1.0/
84 syn/blackboxes/eth_top.v:
-module is now called ethmac instead of eth_top
-eth_defines.v is now called ethmac_defines.v
rfajardo 4001d 15h /minsoc/branches/rc-1.0/
83 minsoc-install.sh: bzip2 program was being used, but its existance on target system was not being verified. It is now. rfajardo 4012d 21h /minsoc/branches/rc-1.0/
82 minsoc-install.sh: problems with copying the GNU Toolchain from download to tools. We uncompress the GNU Toolchain now once again to tools during the installation part. rfajardo 4015d 20h /minsoc/branches/rc-1.0/
81 Installation script complete, nice text feedback, output logs and better execution order. rfajardo 4016d 07h /minsoc/branches/rc-1.0/
80 Establishing a better Makefile system for firmwares. rfajardo 4018d 19h /minsoc/branches/rc-1.0/
79 minsoc-install.sh: rpath corrected.
required-cygwin-tools: updated
rfajardo 4019d 12h /minsoc/branches/rc-1.0/
78 minsoc-install.sh: Advanced JTAG bridge compilation needs to know where the dynamic libraries are on runtime. Patching (sed) the Makefile to compile it with the rpath to the libraries (libusb/libftdi). rfajardo 4019d 12h /minsoc/branches/rc-1.0/
77 New tool requirements for installing Icarus Verilog. rfajardo 4019d 12h /minsoc/branches/rc-1.0/
76 Including a script allowing the installation of MinSoC and all its required tools.

It should be working for all Linuxes and Cygwin.
rfajardo 4019d 13h /minsoc/branches/rc-1.0/
75 Adapting minsoc_top.v and minsoc_verilog_files.txt to new names for top modules and define file of ethmac ip core. rfajardo 4026d 13h /minsoc/branches/rc-1.0/
74 or1200.h includes a CLABLE macro which uses __USER_LABEL_PREFIX__(from compiler defined macro) to find out if we need the underscore as prefix to reference C functions (its assembly labels) or not.

except.S and reset.S use CLABLE to call externally defined C functions.

This should avoid problems compiling firmware with old or new toolchain.

support/common.mk updated, reset-nocache.o and reset-icdc.o are dependent on or1200.h
rfajardo 4119d 11h /minsoc/branches/rc-1.0/
73 Makefile does not automatic clean anymore. In Windows rm -f leads to errors and abort synthesis.

minsoc/syn/setup.bat added. Asks for Xilinx settings32|64.bat script and completely implements MinSoC. On completion or error, it holds window open until user input ENTER.

minsoc/sim/modelsim/: *.bat holds window open until user input ENTER.
run_sim.bat asks for target firmware, check if it exists before running simulator. Holds window open and output error message if not found. Does not hold for simulator.
rfajardo 4119d 16h /minsoc/branches/rc-1.0/
72 Adding Windows batch files to run a Modelsim simulation.
-prepare_modelsim.bat, compile_design.bat, run_sim.bat
rfajardo 4119d 17h /minsoc/branches/rc-1.0/
71 Modelsim whines about missing timescales:
-minsoc_bench.v, minsoc_memory_model.v and dbg_comm_vpi.v updated to include timescale.v

modelsim simulation working under Windows. Modelsim PE Student Edition 10.0a

Simulation<->adv_jtag_bridge<->gdb communication not working perfectly. I believe VPI module has to be recompiled, used pre-compiled one for now.
rfajardo 4119d 20h /minsoc/branches/rc-1.0/
70 Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it.

Removing timescale definition of minsoc_bench_defines.v files.

Creating a modelsim simulation directory. Everything is working under Linux. For Windows, run_sim.sh has to be changed:
-pli ../../bench/verilog/vpi/jp-io-vpi.so
to:
-pli ../../bench/verilog/vpi/jp-io-vpi.dll

These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi.
rfajardo 4119d 20h /minsoc/branches/rc-1.0/
69 backend update:
-minsoc_bench_defines.v
-gcc-opt.mk
Both files should now be under minsoc/backend to proper system functionality.
backend subdirectories have been given those files. Configure script updated accordingly.

They are searched there from system scripts and Makefiles.
-sim/bin/minsoc_verilog_files.txt has the files for Icarus Verilog, minsoc_bench_defines.v is now referenced from backend directory.
-sw/support/Makefile.inc now references to gcc-opt.mk inside backend.

backend/spartan3e_starter_kit_eth:
-It is the system configuration for Spartan 3E Starter Kit with Ethernet.
rfajardo 4124d 12h /minsoc/branches/rc-1.0/
68 Still one configuration mismatch on minsoc_defines.v:
-MEMORY_ADR_WIDTH now 15
-orp.ld is defined accordingly
rfajardo 4126d 16h /minsoc/branches/rc-1.0/
67 Constraint file for backend spartan3a_dsp_kit.ucf was configured to include the STARTUP module.

This module is not enabled under the respective minsoc_defines.v. Thus, its pins had to be commented out.
rfajardo 4126d 16h /minsoc/branches/rc-1.0/
66 spartan3e_starter_kit requires special configuration of or1200_r3.

For that, configure script was specially adapted and that is reported on script execution.

For release-1.0 of MinSoC this should not be required, because or1200_r1 already has the
required configuration.
rfajardo 4126d 17h /minsoc/branches/rc-1.0/

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