URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [backend/] [altera_3c25_board/] - Rev 109

Rev	Log message	Author	Age	Path
109	Creating a branche for release candidate 1.0.	rfajardo	4562d 13h	/minsoc/branches/rc-1.0/backend/altera_3c25_board/
105	Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn.	rfajardo	4562d 23h	/minsoc/branches/rc-1.0/backend/altera_3c25_board/
99	backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails.	rfajardo	4606d 23h	/minsoc/branches/rc-1.0/backend/altera_3c25_board/
97	As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board.	rfajardo	4607d 00h	/minsoc/branches/rc-1.0/backend/altera_3c25_board/
96	Some files needed for Altera synthesis	javieralso	4607d 10h	/minsoc/branches/rc-1.0/backend/altera_3c25_board/
95	Makefile for Altera FPGAs fixed	javieralso	4608d 13h	/minsoc/branches/rc-1.0/backend/altera_3c25_board/
93	Support for Altera synthesis. It needs some tune, but it works fine	javieralso	4611d 01h	/minsoc/branches/rc-1.0/backend/altera_3c25_board/