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[/] [minsoc/] [branches/] [rc-1.0/] [backend/] [altera_3c25_board/] - Rev 130


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124 Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever. rfajardo 3312d 12h /minsoc/branches/rc-1.0/backend/altera_3c25_board/
116 Configure scripts were trying to copy/patch projects files before creating them. Ordering is correct now. rfajardo 3318d 13h /minsoc/branches/rc-1.0/backend/altera_3c25_board/
110 Fixing several minor issues with the system:
-minsoc-install splitted into installation and configuration can be used to configure a fresh checked out system
-configure script used by both and to configure

-rtl/verilog: svn externals fixed
-or1200 rolled back to release-1.0

-Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
-Altera was differentiating it in script
-now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
-altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.

-prj/src: or1200_top.prj downdated to definition of or1200_v1
rfajardo 3319d 06h /minsoc/branches/rc-1.0/backend/altera_3c25_board/
109 Creating a branche for release candidate 1.0. rfajardo 3319d 08h /minsoc/branches/rc-1.0/backend/altera_3c25_board/
105 Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. rfajardo 3319d 18h /minsoc/branches/rc-1.0/backend/altera_3c25_board/
99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 3363d 18h /minsoc/branches/rc-1.0/backend/altera_3c25_board/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 3363d 19h /minsoc/branches/rc-1.0/backend/altera_3c25_board/
96 Some files needed for Altera synthesis javieralso 3364d 06h /minsoc/branches/rc-1.0/backend/altera_3c25_board/
95 Makefile for Altera FPGAs fixed javieralso 3365d 09h /minsoc/branches/rc-1.0/backend/altera_3c25_board/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 3367d 20h /minsoc/branches/rc-1.0/backend/altera_3c25_board/

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