OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [backend/] [altera_3c25_board/] - Rev 143

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
143 Compiling firmwares in board configuration scripts instead of on global minsoc setup. rfajardo 4532d 12h /minsoc/branches/rc-1.0/backend/altera_3c25_board/
124 Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever. rfajardo 4552d 07h /minsoc/branches/rc-1.0/backend/altera_3c25_board/
116 Configure scripts were trying to copy/patch projects files before creating them. Ordering is correct now. rfajardo 4558d 08h /minsoc/branches/rc-1.0/backend/altera_3c25_board/
110 Fixing several minor issues with the system:
-minsoc-install splitted into installation and configuration
-minsoc-configure.sh can be used to configure a fresh checked out system
-configure script used by both minsoc-configure.sh and minsoc-install.sh to configure

-rtl/verilog: svn externals fixed
-or1200 rolled back to release-1.0

-prj/scripts:
-Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
-Altera was differentiating it in script
-now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
-altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.

-prj/src: or1200_top.prj downdated to definition of or1200_v1		 rfajardo 4559d 01h /minsoc/branches/rc-1.0/backend/altera_3c25_board/
109 Creating a branche for release candidate 1.0. rfajardo 4559d 03h /minsoc/branches/rc-1.0/backend/altera_3c25_board/
105 Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. rfajardo 4559d 13h /minsoc/branches/rc-1.0/backend/altera_3c25_board/
99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 4603d 13h /minsoc/branches/rc-1.0/backend/altera_3c25_board/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 4603d 14h /minsoc/branches/rc-1.0/backend/altera_3c25_board/
96 Some files needed for Altera synthesis javieralso 4604d 00h /minsoc/branches/rc-1.0/backend/altera_3c25_board/
95 Makefile for Altera FPGAs fixed javieralso 4605d 03h /minsoc/branches/rc-1.0/backend/altera_3c25_board/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 4607d 15h /minsoc/branches/rc-1.0/backend/altera_3c25_board/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.