OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [backend/] [altera_3c25_board/] [minsoc_defines.v] - Rev 109

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
109 Creating a branche for release candidate 1.0. rfajardo 4765d 13h /minsoc/branches/rc-1.0/backend/altera_3c25_board/minsoc_defines.v
99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 4809d 23h /minsoc/branches/rc-1.0/backend/altera_3c25_board/minsoc_defines.v
95 Makefile for Altera FPGAs fixed javieralso 4811d 14h /minsoc/branches/rc-1.0/backend/altera_3c25_board/minsoc_defines.v
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 4814d 01h /minsoc/branches/rc-1.0/backend/altera_3c25_board/minsoc_defines.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.