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[/] [minsoc/] [branches/] [rc-1.0/] [backend/] [std/] [minsoc_defines.v] - Rev 57

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57 If a FPGA manufacturer is selected, the FPGA families of other manufacturers are automatically ignored.

Some updated to comments.

CLOCK_DIVISOR back to 5. The number does not matter much, but 1 is a bad standard number, since it should never be selected. Comment says, use NO_CLOCK_DIVISION instead.

Changing standard FPGA back to Xilinx and Spartan3A. I'm only doing this because the synthesis examples page of wiki still assume this FPGA to be standardly selected.		 rfajardo 4739d 03h /minsoc/branches/rc-1.0/backend/std/minsoc_defines.v
56 Macros for all Altera family devices and pll instantiation javieralso 4746d 02h /minsoc/branches/rc-1.0/backend/std/minsoc_defines.v
52 Altera ALTPLL Megafunction Instantiation javieralso 4756d 03h /minsoc/branches/rc-1.0/backend/std/minsoc_defines.v
20 minsoc_defines.v had a semicolon at the end of the two reset polarity definitions.

minsoc_top had a signal array for two different signals which was for backward compatibility. The compatible debugging module is so old that there is no reason for keeping it.

Documentation has been updated to better explain how to use the definitions files, minsoc_defines.v and or1200_defines.v. An example for Altera devices has been added too.		 rfajardo 5201d 10h /minsoc/branches/rc-1.0/backend/std/minsoc_defines.v
7 Some changes:
-wb_cabs removed from minsoc_top.v and minsoc_tc_top.v
-added reset polarity control to minsoc_defines.v through:
-POSITIVE_RESET
-NEGATIVE_RESET
-minsoc_onchip_ram_top.v does not use
minsoc_onchip_ram.v oe signals (output enable) anymore,
which are implemented as tristate buffers. Now
minsoc_onchip_ram_top.v has a generated MUX, which
has an arbitrary number of inputs and 1 output.
Input are the internal output of the onchip_rams,
output the wb_dat_o.		 rfajardo 5312d 08h /minsoc/branches/rc-1.0/backend/std/minsoc_defines.v
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit		 rfajardo 5326d 13h /minsoc/branches/rc-1.0/backend/std/minsoc_defines.v

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