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[/] [minsoc/] [branches/] [rc-1.0/] [prj/] [altera/] - Rev 130

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Rev Log message Author Age Path
109 Creating a branche for release candidate 1.0. rfajardo 3319d 22h /minsoc/branches/rc-1.0/prj/altera/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 3364d 09h /minsoc/branches/rc-1.0/prj/altera/
96 Some files needed for Altera synthesis javieralso 3364d 19h /minsoc/branches/rc-1.0/prj/altera/
95 Makefile for Altera FPGAs fixed javieralso 3365d 22h /minsoc/branches/rc-1.0/prj/altera/
94 Fix bug in minsoc_top.prj for Altera synthesis javieralso 3368d 07h /minsoc/branches/rc-1.0/prj/altera/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 3368d 10h /minsoc/branches/rc-1.0/prj/altera/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 3370d 02h /minsoc/branches/rc-1.0/prj/altera/

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