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109 Creating a branche for release candidate 1.0. rfajardo 3860d 21h /minsoc/branches/rc-1.0/prj/scripts/
108 Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.

Icarus Verilog and Altera synthesis are working as well. Job done!
rfajardo 3861d 01h /minsoc/branches/rc-1.0/prj/scripts/
107 Adding setup batch script for Altera synthesis on Windows.

prj/scripts/altprj.sh has now to check if it is run from cygwin in order to re-formulate the path to windows system.

Maybe the other scripts have to be updated too. This will be checked soon.
rfajardo 3861d 04h /minsoc/branches/rc-1.0/prj/scripts/
104 Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools)
rfajardo 3868d 07h /minsoc/branches/rc-1.0/prj/scripts/
96 Some files needed for Altera synthesis javieralso 3905d 19h /minsoc/branches/rc-1.0/prj/scripts/
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 3910d 09h /minsoc/branches/rc-1.0/prj/scripts/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 3911d 00h /minsoc/branches/rc-1.0/prj/scripts/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 3911d 02h /minsoc/branches/rc-1.0/prj/scripts/

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