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[/] [minsoc/] [branches/] [rc-1.0/] [prj/] [scripts/] [xilinxprj.sh] - Rev 109

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109 Creating a branche for release candidate 1.0. rfajardo 3857d 13h /minsoc/branches/rc-1.0/prj/scripts/xilinxprj.sh
108 Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.

Icarus Verilog and Altera synthesis are working as well. Job done!
rfajardo 3857d 16h /minsoc/branches/rc-1.0/prj/scripts/xilinxprj.sh
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 3907d 00h /minsoc/branches/rc-1.0/prj/scripts/xilinxprj.sh
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 3907d 15h /minsoc/branches/rc-1.0/prj/scripts/xilinxprj.sh
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 3907d 17h /minsoc/branches/rc-1.0/prj/scripts/xilinxprj.sh

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