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[/] [minsoc/] [branches/] [rc-1.0/] [prj/] [src/] - Rev 110

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Rev Log message Author Age Path
110 Fixing several minor issues with the system:
-minsoc-install splitted into installation and configuration
-minsoc-configure.sh can be used to configure a fresh checked out system
-configure script used by both minsoc-configure.sh and minsoc-install.sh to configure

-rtl/verilog: svn externals fixed
-or1200 rolled back to release-1.0

-prj/scripts:
-Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
-Altera was differentiating it in script
-now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
-altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.

-prj/src: or1200_top.prj downdated to definition of or1200_v1
rfajardo 3689d 03h /minsoc/branches/rc-1.0/prj/src/
109 Creating a branche for release candidate 1.0. rfajardo 3689d 05h /minsoc/branches/rc-1.0/prj/src/
96 Some files needed for Altera synthesis javieralso 3734d 03h /minsoc/branches/rc-1.0/prj/src/
89 minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. rfajardo 3739d 08h /minsoc/branches/rc-1.0/prj/src/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 3739d 08h /minsoc/branches/rc-1.0/prj/src/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 3739d 09h /minsoc/branches/rc-1.0/prj/src/

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