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[/] [minsoc/] [branches/] [rc-1.0/] [rtl/] [verilog/] [minsoc_clock_manager.v] - Rev 153

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109 Creating a branche for release candidate 1.0. rfajardo 4731d 07h /minsoc/branches/rc-1.0/rtl/verilog/minsoc_clock_manager.v
62 Wrapping different family modules of same manufacturer in a single module.

minsoc_clock_manager.v: uses fpga manufacturer wrappers

xilinx_dcm.v: selects between different Xilinx FPGA families and implements the module

altera_pll.v: selects between different Altera FPGA families and implements the module
rfajardo 4911d 16h /minsoc/branches/rc-1.0/rtl/verilog/minsoc_clock_manager.v
56 Macros for all Altera family devices and pll instantiation javieralso 4919d 04h /minsoc/branches/rc-1.0/rtl/verilog/minsoc_clock_manager.v
52 Altera ALTPLL Megafunction Instantiation javieralso 4929d 05h /minsoc/branches/rc-1.0/rtl/verilog/minsoc_clock_manager.v
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 5499d 15h /minsoc/branches/rc-1.0/rtl/verilog/minsoc_clock_manager.v

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