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109 Creating a branche for release candidate 1.0. rfajardo 3377d 07h /minsoc/branches/rc-1.0/rtl/verilog/minsoc_startup/
12 1) spi_top.v:
-TX_NEGEDGE bug reported and recommended solution by Blaise Gassend. (Thank you)
2) minsoc howto extended to:
-synthesis of minsoc for Spartan3E Starter Kit with Ethernet
3) spartan3e_starter_kit.ucf changed:
-it had problems regarding pin definitions and IO logic types for mapping and place&route. Working flawless now.
rfajardo 4103d 08h /minsoc/branches/rc-1.0/rtl/verilog/minsoc_startup/
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 4145d 15h /minsoc/branches/rc-1.0/rtl/verilog/minsoc_startup/

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